Buried Bitline 4F2 Vertical DRAM for Low-Resistance Scaling
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Solution Overview
Problem
Current 4F2 DRAM devices face high bitline resistance due to the scaling of semiconductor structures, which affects the patterning and formation of three-dimensional structures, including trenches for storage nodes and access transistors.
Innovation Solution
The implementation of buried metal bitlines formed using an implantation process followed by an angled etch process, which reduces bitline resistance by connecting every two pillars to a buried metal bitline and forming merged metal gates perpendicular to the bitlines, aligning them with pillar direction and connecting on different levels vertically to enable high-speed 4F2 DRAM operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertical semiconductor fin structures with high aspect ratios are used to scale DRAM devices, then device density is improved, but bitline resistance increases
Solution Approach 1:
The patent transitions from planar bitlines to three-dimensional buried bitlines that extend beneath vertical fin structures. This dimensional change allows bitlines to maintain low resistance by providing multiple conduction paths through the vertical dimension, compensating for the increased aspect ratio of scaled devices.
Solution Approach 2:
The patent introduces merged metal gates as intermediary structures that serve dual functions: controlling the vertical fins and providing low-resistance horizontal conduction paths. These metal gates act as mediators between the bitline nodes, reducing overall bitline resistance while maintaining device scaling.
2Manufacturing precision
If monocrystalline silicon vertical fin structures are used, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple metal gate structures into unified buried bitline formations. By combining the gate control function with the bitline conduction function into integrated metal gate structures, the design reduces overall device complexity while maintaining the precision benefits of monocrystalline silicon fins.
Solution Approach 2:
The metal gate structures serve multiple functions simultaneously: they provide electrical control over the vertical fins, act as low-resistance bitline conduits, and enable horizontal current flow paths. This multi-functionality reduces the number of separate components needed, simplifying the overall device structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces bitline resistance, ensures every two pillars are connected to a buried metal bitline, and allows for high-speed 4F2 DRAM operations by aligning bitlines and wordlines with pillar direction, thus enhancing the performance of 4F2 DRAM devices.
Implementation Method 1
removing the dielectric film by performing an angled ion etch oriented at a non-zero angle relative to a perpendicular extending from an upper surface of the plurality of vertical structures, wherein ions of the angled ion etch are directed into a first side and the upper surface of the plurality of vertical structures of the saddle area without being directed into a second side of the plurality of vertical structures of the saddle area
Data Source
AI summary
Disclosed are approaches for forming 4F2 vertical DRAM devices including buried bitlines. One DRAM device may include a plurality of bitlines between a plurality of vertical structures extending from a substrate, and a bottom source/drain formed in each of the plurality of vertical structures in a saddle area, wherein the saddle area comprises a saddle trench formed through the plurality of vertical structures. The DRAM device may further include a dielectric film formed over the plurality of vertical structures in the saddle area, wherein the dielectric film is present along a portion of the plurality of bitlines and along just a first sidewall the plurality of vertical structures in the saddle area, and a fill material over the plurality of vertical structures of the saddle area, wherein the fill material directly contacts the plurality of bitlines.