Buried Breakdown Thyristor ESD Protection Device
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Solution Overview
Problem
Integrated circuits (ICs) are vulnerable to damage from electrostatic discharge (ESD) events, which can cause high current densities near the substrate surface, leading to potential device failures and hot spots, and existing ESD protection devices may interfere with normal IC operation or require larger footprints.
Innovation Solution
The implementation of ESD protection devices with a thyristor arrangement featuring a buried breakdown junction, where the breakdown current path is established through a buried doped layer and base regions, avoiding high current densities near the surface and allowing for adjustable trigger voltages, thus providing robust ESD protection without increasing device size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ESD protection devices are configured to provide another path to ground for discharge current, then device reliability during ESD events is improved, but high current densities near the substrate surface cause hot spots and potential device failures
Solution Approach 1:
The patent moves the breakdown junction from the substrate surface to a buried location within the substrate bulk. This dimensional relocation of the current path from surface-level to subsurface eliminates the harmful concentration of current density at the surface, preventing hot spots while maintaining ESD protection functionality through the buried breakdown thyristor structure
Solution Approach 2:
The patent introduces a buried doped layer as an intermediary structure that facilitates controlled breakdown at a specific location within the substrate. This buried layer acts as a mediator that redirects the discharge current through the substrate bulk rather than allowing surface-level current concentration, thereby protecting against hot spots while enabling ESD protection
2Ease of operation
If ESD protection devices use a triggering voltage above the normal operating range, then normal IC operation is not interfered with, but the device footprint increases
Solution Approach 1:
The patent utilizes the buried breakdown thyristor structure to achieve a compact design with reduced footprint while maintaining the triggering voltage parameter above the normal operating range. The vertical integration of the breakdown junction into the substrate bulk allows for smaller lateral dimensions, enabling compact ESD protection devices that do not interfere with normal IC operation
Solution Approach 2:
The patent embeds the ESD protection structure within the existing substrate architecture by creating a buried breakdown junction that utilizes the substrate's vertical space. This nesting approach integrates the protection device into the substrate's three-dimensional structure, reducing the lateral footprint while maintaining the required triggering voltage characteristics
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively prevents device failures during ESD events by routing the current through the substrate bulk, reducing the risk of hot spots and maintaining device integrity while allowing for compact design and adaptability to various operating voltages.
Implementation Method 1
breakdown at a first junction along the inner sinker region
Data Source
AI summary
An electrostatic discharge protection device includes a substrate, first and second emitter regions disposed in the substrate, laterally spaced from one another on a side of the substrate, and having opposite conductivity types, and first and second base regions having opposite conductivity types and in which the first and second emitter regions are disposed in a thyristor arrangement, respectively. The first base region includes a buried doped layer that extends under the second base region. Each of the buried doped layer and the second base region includes a respective non-uniformity in dopant concentration profile. A spacing between the buried doped layer and the second base region at the respective non-uniformities establishes a breakdown trigger voltage for the thyristor arrangement.