Buried Cavity Matrix for RF SOI Circuit Linearity

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Solution Overview

Problem

RF electronic circuits on SOI substrates face performance limitations due to residual surface charges at the interface between the buried oxide layer and the silicon support layer, with existing solutions being either expensive or requiring complex double transfer processes.

Innovation Solution

A matrix of buried cavities in the substrate beneath the RF electronic components, which increases electrical resistance and reduces the impact of residual surface charges, while maintaining mechanical and thermal properties, and is cost-effective without requiring double substrate transfers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a polysilicon layer is inserted between the silicon support layer and the buried dielectric layer to reduce charge dynamics, then harmonic distortions are significantly reduced, but manufacturing cost increases

Engineering Contradiction:

ImprovelinearityVSAvoidmanufacturing cost

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent replaces the expensive polysilicon layer with a simplified structure using only the existing silicon support layer with controlled thickness and cavity configuration, achieving the same charge isolation effect at lower manufacturing cost

Inventive Principle:

Principle #27Cheap short-living objects (Disposable)

Solution Approach 2:

The patent changes the geometric parameters of the support layer (thickness between 1-10 μm) and introduces cavity structures to modify the electrical characteristics, replacing the need for additional polysilicon material layer

Inventive Principle:

Principle #35Parameter changes

2Reliability

If the Ultimate-Thinning-and-Transfer-Bonding process is used to replace the silicon support layer, then electrical performances are improved, but device complexity increases due to requiring two transfers

Engineering Contradiction:

Improveelectrical performanceVSAvoidprocess complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts and removes the problematic interface between the silicon support layer and buried dielectric layer by creating cavities and thinning the support layer, eliminating the charge accumulation issue without requiring complex transfer processes

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces a vertical dimension solution by controlling support layer thickness (1-10 μm) and creating cavity structures, transforming the problem from a material composition issue to a geometric configuration issue

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Reliability

If the support layer thickness is reduced to increase electrical resistance, then linearity improves, but mechanical strength decreases

Engineering Contradiction:

ImprovelinearityVSAvoidmechanical strength

Core Design Contradiction:

ReliabilityVSStrength

Solution Approach 1:

The patent segments the support layer by introducing cavity structures within it, creating isolated regions that provide mechanical reinforcement while maintaining the overall thin profile needed for electrical performance

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent creates a composite structure where the support layer combines silicon material with cavity spaces, achieving both the electrical resistance characteristics of a thin layer and the mechanical strength of a more substantial structure

Inventive Principle:

Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The matrix of cavities enhances the linearity and electrical performance of RF components by isolating them from residual surface charges, improving thermal and mechanical properties, and simplifying manufacturing processes.

Implementation Method 1

the cavities reduce the volume of material located under the RF electronic components) and increase the electrical resistance between the support layer and the electronic component(s)

Methodology Applied

Scientific EffectElectrical Resistance: Electrical Resistance

Implementation Method 2

the electrical performances (particularly the linearity) of an RF electronic circuit made on an SOI substrate are limited by residual surface charges located at the interface between the Buried Oxide (BOX) layer and the solid layer or support layer

Methodology Applied

Scientific EffectElectrostatics: Electrostatics

Data Source

PatentUS10431597B2RF electronic circuit comprising cavities buried under RF electronic components of the circuit

Publication Date: 2019.10.01 COMMISSARIAT A LENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

AI summary

An RF electronic circuit comprising at least: a substrate comprising at least one support layer and a semiconducting surface layer located on the support layer; at least one electronic component able to carry out at least one of the RF signal transmission and/or reception and/or processing functions, and made in or on a first region of the surface layer; and a matrix of cavities located in at least one first region of the support layer located under the first region of the surface layer, facing at least the electronic component, and such that the internal volumes of the cavities are separated and isolated from each other by portions of the support layer.