Buried Cavity Formation via Selective Doping Etching
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Solution Overview
Problem
Current methods for electrical and mechanical decoupling of regions on semiconductor substrates, such as silicon wafers, are costly, inflexible, and can damage filigree structures, limiting the integration of multiple functional blocks on a single carrier.
Innovation Solution
A method involving dopant implantation to create doped volume regions with increased etching rates, allowing for the formation of buried cavity structures through access openings, enabling precise and cost-effective decoupling without thermal stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the Venezia process or SON process is used to produce local cavities for decoupling, then electrical and mechanical decoupling is achieved, but the process becomes cost intensive and requires subsequent CMP process steps that can impair or destroy filigree structures
Solution Approach 1:
The patent changes the etching rate parameter of specific regions by doping the semiconductor substrate with phosphorus or arsenic. This creates selective etching zones that can be removed to form cavities without requiring the complex Venezia or SON processes, thereby reducing manufacturing complexity and cost while maintaining decoupling effectiveness
Solution Approach 2:
The patent introduces a dopant (phosphorus or arsenic) as an intermediary substance that modifies the local etching properties of the semiconductor substrate. This intermediary enables selective material removal through chemical etching, avoiding the need for complex mechanical or thermal processes that would increase manufacturing complexity
2Reliability
If high process temperatures are applied for the Venezia approach, then local cavities can be produced, but functional elements integrated later are no longer permitted to be subjected to such thermal loading
Solution Approach 1:
The patent replaces thermal processing (high-temperature Venezia process) with chemical processing (selective etching of doped regions). This substitution allows cavity formation at lower temperatures that are compatible with subsequently integrated functional elements, while maintaining the ability to produce well-defined cavities for decoupling
Solution Approach 2:
The patent changes the etching selectivity parameter by modifying the chemical composition of specific substrate regions through doping. This enables selective removal of material at low temperatures by using etchants that react preferentially with the doped regions, avoiding thermal damage to sensitive functional elements
3Reliability
If local or whole area thinning of the basic material is carried out for decoupling, then electrical and mechanical decoupling is achieved, but the process lacks flexibility in terms of position and implementation
Solution Approach 1:
The patent applies local quality by doping only specific regions of the semiconductor substrate with phosphorus or arsenic. This creates localized zones with modified etching properties that can be selectively removed to form cavities at precise positions, enabling flexible and adaptable decoupling structures throughout the substrate without requiring uniform thinning
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for flexible and cost-effective electrical and mechanical decoupling, preserving the integrity of structures and enabling the integration of multiple functional elements on a single semiconductor substrate.
Implementation Method 1
producing a doped volume region in the monocrystalline semiconductor substrate by means of a dopant implantation
Implementation Method 2
removing the doped semiconductor material in the doped volume region using the first etchant through the access opening
Implementation Method 3
a step of epitaxially depositing a monocrystalline semiconductor layer on the first main surface region of the monocrystalline semiconductor substrate is carried out in order to obtain an increase in thickness with an additional monocrystalline semiconductor material
Data Source
AI summary
In accordance with an embodiment, a method for producing a buried cavity structure includes providing a mono-crystalline semiconductor substrate, producing a doped volume region in the mono-crystalline semiconductor substrate, wherein the doped volume region has an increased etching rate for a first etchant by comparison with an adjoining, undoped or more lightly doped material of the monocrystalline semiconductor substrate, forming an access opening to the doped volume region, and removing the doped semiconductor material in the doped volume region using the first etchant through the access opening to obtain the buried cavity structure.