Buried-Channel Drain Transistor for CCD Amplifier Glow Reduction
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Solution Overview
Problem
Conventional load transistors in CCD imaging systems experience high voltage drops and electric fields at the drain terminals, leading to reduced breakdown voltage and unwanted light emission, known as amplifier glow, which affects image quality.
Innovation Solution
The implementation of a buried-channel drain (BCD) transistor structure with a lightly-doped buried channel layer at the drain end of the gate, reducing the maximum electric field and increasing the drain-to-source breakdown voltage, achieved through ion implantation and optional use of an oxide spacer to self-align the source-drain layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional load transistor with self-aligned n+ source and drains is used, then the transistor can be manufactured with standard processes, but the breakdown voltage is substantially less than the 10 V voltage drop due to high electric fields at the drain
Solution Approach 1:
The patent applies local quality by creating a buried-channel region with different doping characteristics specifically at the drain end of the transistor channel. This localized modification of the channel structure reduces the electric field concentration at the drain junction, thereby increasing the breakdown voltage without requiring a complete redesign of the entire transistor structure. The buried-channel region is formed with lighter doping compared to the surface channel, providing field reduction precisely where needed.
Solution Approach 2:
The patent introduces a vertical dimension to the channel structure by forming a buried-channel region beneath the surface channel. This third-dimensional approach (moving from a two-dimensional surface channel to a three-dimensional structure with depth) allows the electric field to be distributed through the vertical dimension, reducing the peak field intensity at the drain junction and increasing breakdown voltage.
2Reliability
If a conventional load transistor is used, then the manufacturing process remains simple, but light is emitted from the current load transistor due to high electric fields at the drain terminals, manifesting as undesired glow in the final image
Solution Approach 1:
The buried-channel region is localized specifically at the drain end of the transistor, creating a zone with reduced electric field intensity. This local modification prevents carrier multiplication and light emission (amplifier glow) at the critical drain junction without affecting other parts of the transistor. The selective placement of the buried-channel region targets the specific problem area where glow occurs.
3Reliability
If ion implantation is used to form the buried-channel drain region, then the breakdown voltage is increased and reliability is enhanced, but the manufacturing process becomes more complex
Solution Approach 1:
The buried-channel drain region is formed through ion implantation as a preliminary step before final transistor fabrication. By establishing the buried-channel structure early in the manufacturing sequence, subsequent processing steps can proceed with standard techniques, and the beneficial breakdown voltage enhancement is already in place before final device assembly. This preliminary action allows the complex step to be performed once rather than requiring complex modifications later.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances the reliability and breakdown voltage of the load transistor, reducing amplifier glow and improving image quality by minimizing electric fields at the drain edge, while being suitable for devices with longer channel lengths and simpler processing.
Implementation Method 1
The buried-channel drain region may be formed via ion implantation either before or after patterning of the gate conductor
Data Source
AI summary
A charge-coupled device (CCD) image sensor is provided. The CCD image sensor may include an array of photosensors that transfer charge to multiple vertical CCD shift registers, which then in turn transfer the charge to a horizontal CCD shift register. The horizontal CCD shift register then feeds an output buffer circuit. The output buffer circuit can include a load transistor implemented using a buried-channel drain (BCD) structure. The load transistor may include a gate conductor, a source diffusion region, a drain diffusion region, and a buried-channel drain region that at least partially extends under the gate conductor. The BCD region may be formed before or after the formation of the gate conductor. If desired, the BCD region can also be formed at the source edge. An image sensor configured in this way can exhibit higher source-drain breakdown voltages, enhanced amplifier gain, and reduced amplifier glow.