Buried-Channel Transistor Doping Layout for Low 1/f Noise
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Solution Overview
Problem
Conventional buried channel transistors that deeply bury the channel region in the semiconductor substrate to reduce 1/f noise experience an increase in the short-channel effect, which degrades performance.
Innovation Solution
A semiconductor apparatus with a buried region comprising a p-type first region and an n-type second region, where the first region is buried at least 50 nm deep and the second region is located between the first region and the gate insulating film, with specific impurity concentrations and distributions to enhance channel burial and reduce interface state density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the channel region is deeply buried in the semiconductor substrate to reduce 1/f noise, then 1/f noise is reduced, but the short-channel effect increases
Solution Approach 1:
The patent divides the channel region into multiple segments along the depth direction: a first channel region extending from the surface to a first depth, and a second channel region extending from the first depth to a second depth. This segmentation allows different portions of the channel to have different impurity concentrations and electrical characteristics, enabling the channel to be buried deep enough to reduce 1/f noise while maintaining control over the short-channel effect through differentiated doping profiles in each segment
Solution Approach 2:
The patent applies local quality by creating distinct impurity concentration profiles in different regions of the channel. The first channel region has a first impurity concentration while the second channel region has a second impurity concentration. This local differentiation allows the upper channel region to maintain better electrical control (reducing short-channel effect) while the overall channel is buried deeply in the substrate (reducing 1/f noise)
2Object-affected harmful factors
If the channel region is deeply buried in the semiconductor substrate, then interface state density is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent employs preliminary action through selective epitaxial growth to form the channel region at controlled depths before final device assembly. By pre-forming the channel structure with appropriate burial depth and impurity distribution through epitaxial growth, the interface state density is reduced while the manufacturing process remains systematic and controllable, avoiding the need for complex post-processing steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration suppresses the short-channel effect while effectively reducing 1/f noise by increasing the burial depth of the channel, thereby improving the transistor's performance and reducing off-leakage current.
Implementation Method 1
a well region of a first conductivity type located on a surface layer of a semiconductor substrate; a source region of a second conductivity type and a drain region of the second conductivity type located on a surface layer of the well region; a first region of the second conductivity type located between the source region and the drain region and buried in the well region; and a second region of the first conductivity type located between the first region and the gate insulating film
Data Source
AI summary
A semiconductor apparatus includes a gate insulating film, a well region of a first conductivity type located on a surface layer of a semiconductor substrate, a source region of a second conductivity type and a drain region of the second conductivity type located on a surface layer of the well region, a first region of the second conductivity type, and a second region of the first conductivity type. The first region is located between the source region and the drain region and is buried in the well region. The second region is located between the first region and the gate insulating film. A burying depth of the first region in the well region from the surface of the semiconductor substrate is 50 nm or more.