Buried Chip Substrate Layout Without Conductive Blind Holes
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Solution Overview
Problem
Substrates with buried components face limitations in design flexibility and increased noise and power loss due to the need for conductive blind holes for chip component connections, which occupy more space and reduce the flexibility of circuit layer structures.
Innovation Solution
A substrate with a buried component featuring a composite inner layer circuit structure where the chip component penetrates multiple circuit layers, with surface bonding pads directly connected to component connecting ends, eliminating the need for conductive blind holes and allowing for vertical connection to the circuit layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If chip component is disposed in the circuit layer structure with conductive blind holes for connection, then the chip component can be electrically connected to the circuit layer, but the path for connecting chip components increases causing noise gain, power loss, and reduced design flexibility
Solution Approach 1:
The patent extracts and eliminates the conductive blind holes from the connection path between chip components. By providing component connecting ends that protrude from the circuit layer structure, the invention creates a direct connection path that bypasses the need for conductive blind holes, thereby removing the source of noise and power loss while maintaining electrical connection reliability
Solution Approach 2:
The patent transitions from a two-dimensional planar connection approach to a three-dimensional vertical integration approach. Component connecting ends protrude from the circuit layer structure in the vertical dimension, allowing chip components to be connected directly without requiring horizontal path routing through conductive blind holes, thus reducing connection path length and eliminating noise and power loss
2Ease of operation
If chip component occupies more areas of the circuit layer structure, then the chip component can be properly disposed and connected, but the flexibility of the circuit substrate is limited
Solution Approach 1:
The patent utilizes vertical integration by allowing component connecting ends to protrude from the circuit layer structure. This three-dimensional approach enables chip components to be disposed and connected with reduced horizontal space requirements, thereby maintaining circuit substrate flexibility while ensuring proper chip component disposal and connection
3Reliability
If conductive blind holes are used for connecting chip components, then electrical connection can be established, but the path for connecting increases causing space expansion and reduced design flexibility
Solution Approach 1:
The patent removes conductive blind holes from the connection architecture by providing component connecting ends that protrude from the circuit layer structure. This extraction simplifies the connection path between chip components, eliminating the need for complex multi-layer blind hole routing while maintaining reliable electrical connection
Solution Approach 2:
Instead of routing connections horizontally through conductive blind holes within the circuit layer structure, the patent inverts the approach by having component connecting ends protrude vertically from the circuit layer. This inversion creates a simpler, more direct connection path that reduces device complexity while ensuring reliable electrical connection
Data Source
AI summary
A substrate is manufactured by drilling a chip containing groove in a composite inner layer circuit structure, having a component connecting end of a circuit layer protruding from a mounting side wall in the chip containing groove, mounting a chip component in the chip containing groove, and connecting the surface bonding pad to the component connecting end. The chip component in the present invention penetrates at least two circuit layers, and the surface bonding pad is bonded to the component connecting end of the circuit layer directly, reducing the occupied area of the chip component in each one of the circuit layers, and increasing the area for circuit disposing and the possible amount of chip components that may be mounted in the substrate.