Buried Comb-Electrode Capacitive Element for High-Density Circuit Carriers

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Solution Overview

Problem

The challenge of integrating high-capacitance buried capacitive elements in high-density circuit boards within limited space is unresolved, impacting the functionality and performance of electronic products.

Innovation Solution

A circuit carrier design incorporating a capacitive element with a comb-like inter-electrode structure, comprising lower and upper electrodes with interdigitated fingers, and distinct interlayer dielectrics to enhance capacitance and reduce space requirements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If a traditional capacitive element is used in circuit board design, then the structure is simple and easy to manufacture, but the capacitance is insufficient in limited space

Engineering Contradiction:
ImprovecapacitanceVSAvoidspace
Core Design Contradiction:
Quantity of substanceVSArea of stationary object

Solution Approach 1:

The capacitive element is divided into multiple segments: a lower electrode with multiple fingers, an upper electrode with multiple fingers, and an inter-electrode with fingers extending from both sides. This segmentation increases the effective capacitance area within a compact footprint by creating multiple overlapping electrode pairs vertically stacked in the dielectric layers.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from a planar two-dimensional electrode arrangement to a three-dimensional stacked configuration. The lower electrode, inter-electrode, and upper electrode are arranged in vertical layers with fingers extending in multiple directions, utilizing the third dimension (depth/thickness) to maximize capacitance density within limited horizontal space.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If the number of passive components is increased to meet multi-functionality requirements, then the functionality is enhanced, but the component density and space utilization become problematic

Engineering Contradiction:
ImprovefunctionalityVSAvoidcomponent density
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent combines multiple electrode functions into a single integrated capacitive element structure. The lower electrode, inter-electrode, and upper electrode with their respective fingers form a unified multi-capacitance component that provides enhanced functionality while occupying minimal space, thereby increasing component density without sacrificing versatility.

Inventive Principle:
Principle #5Merging (Combining)

3Length of stationary object

If the circuit carrier is made thinner to reduce size, then the profile is compact, but the available space for capacitive elements is reduced

Engineering Contradiction:
ImprovethicknessVSAvoidcapacitance
Core Design Contradiction:
Length of stationary objectVSQuantity of substance

Solution Approach 1:

The patent maximizes capacitance within a thin profile by utilizing vertical stacking of electrodes in multiple dielectric layers. The lower electrode, inter-electrode, and upper electrode are positioned at different vertical levels, creating overlapping finger structures that generate capacitance in the vertical dimension rather than requiring additional horizontal or thickness space.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The design achieves higher equivalent capacitance and facilitates thinner circuit carriers by optimizing electrode placement and dielectric materials, addressing the space constraints in high-density circuit boards.

Implementation Method 1

a capacitive element includes a lower electrode, an inter-electrode and an upper electrode. The inter-electrode is located between the lower electrode and the upper electrode

Methodology Applied
Scientific EffectCapacitance: Capacitance

Implementation Method 2

The capacitive element is disposed in at least one dielectric layer of the wiring layer

Methodology Applied
Scientific EffectDielectric: Dielectric

Data Source

PatentUS12621933B2Capacitive element, circuit carrier having the same and fabrication method thereof
Publication Date: 2026.05.05 UNIMICRON TECH CORP
  • US12621933B2 patent drawing
  • US12621933B2 patent drawing
  • US12621933B2 patent drawing

AI summary

A circuit carrier includes at least one wiring layer and a capacitive element. The capacitive element is disposed in at least one dielectric layer of the wiring layer. The capacitive element includes a lower electrode, an inter-electrode and an upper electrode. The inter-electrode is located between the lower electrode and the upper electrode. The inter-electrode includes a plate, at least one first finger and at least one second finger. The first finger and the second finger extend from opposite sides of the plate, respectively.