Buried Conductive Ferroelectric Memory via Ion Implantation
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Solution Overview
Problem
Ferroelectric memory devices face challenges in miniaturization due to the damage caused by semiconductor etching processes, leading to deterioration of ferroelectric performance and reduced information retention, especially in pattern-forming ferroelectric memory units with programming projected block structures.
Innovation Solution
A non-volatile ferroelectric memory design incorporating buried conductive layers formed through blackening, diffusion, or ion implantation treatments on the surface of the ferroelectric storage layer, which reduces the need for semiconductor etching and enhances the conductivity and retention of the ferroelectric domain, allowing for improved storage performance and scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If semiconductor etching process is used to form programming projected block structure, then ferroelectric memory units can be patterned, but ferroelectric material is damaged and ferroelectric performance deteriorates
Solution Approach 1:
The patent extracts the harmful etching process from the fabrication sequence and replaces it with a deposition-based approach. Conductive layers are deposited conformally on the ferroelectric surface and then planarized, eliminating the need for pattern etching that damages the ferroelectric material while still achieving the required structural differentiation.
Solution Approach 2:
The patent introduces planarization layers (such as spin-on-glass or other dielectric materials) as intermediaries between the ferroelectric layer and the conductive layers. This mediator allows for subsequent processing steps to be performed on a planar surface without directly exposing or damaging the underlying ferroelectric material, thus preserving its performance while enabling precise patterning.
2Length of moving object
If semiconductor etching process is used to form programming projected block structure, then memory units can be miniaturized, but information retention is reduced
Solution Approach 1:
The patent removes the etching step that causes material damage and replaces it with conformal deposition and planarization techniques. This allows for the formation of scaled-down memory structures without the harmful effects of etching, thereby maintaining information retention capabilities while achieving miniaturization.
Solution Approach 2:
The patent changes the fabrication parameters from etching-based material removal to deposition-based material addition and planarization. This parameter change enables the creation of smaller feature sizes through controlled deposition thickness and planarization precision, rather than through etching depth, thus preserving ferroelectric integrity while achieving miniaturization.
3Ease of manufacture
If conventional electrode structure is used, then manufacturing is simple, but read current is insufficient for reliable data reading
Solution Approach 1:
The patent segments the electrode structure into multiple functional layers: bottom electrode, intermediate conductive layers with specific resistance values, and top electrode. This segmentation allows each layer to be optimized for its specific function - the intermediate layers with controlled resistance (10^3-10^6 ohm·cm²) serve as current amplification stages, thereby increasing the read current without complicating the overall manufacturing process.
Solution Approach 2:
The patent employs composite electrode structures combining different materials with distinct electrical properties. The intermediate conductive layers use materials with specific resistance characteristics (10^3-10^6 ohm·cm²) that differ from the bottom and top electrodes. This composite structure enables current amplification while maintaining compatibility with standard semiconductor fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively increases the on-state read current and data retention while minimizing damage to the ferroelectric material, enabling smaller, more efficient, and higher-density memory devices with reduced write and read power consumption.
Implementation Method 1
the buried conductive layer is formed by partially performing blackening treatment, diffusion treatment, or ion implantation treatment on the surface of the ferroelectric storage layer
Implementation Method 2
the buried conductive layer is formed by partially performing blackening treatment, diffusion treatment, or ion implantation treatment on the surface of the ferroelectric storage layer
Implementation Method 3
the buried conductive layer is formed by partially performing blackening treatment, diffusion treatment, or ion implantation treatment on the surface of the ferroelectric storage layer
Data Source
AI summary
The present disclosure relates to a non-volatile ferroelectric memory and a method of preparing the same. The ferroelectric memory includes a ferroelectric storage layer, a first electrode and a second electrode; the first electrode and the second electrode each include a buried conductive layer formed by patterning in a surface of the ferroelectric storage layer and an electrode layer formed on the buried conductive layer; and when a write signal in a certain direction is applied between the first electrode and the second electrode, the electric domains of a part of the ferroelectric storage layer between a pair of the buried conductive layers are enabled to be reversed, so that a domain wall conductive passage that electrically connects the first electrode and the second electrode can be established.