Buried Conductive Line in Semiconductor Isolation Structure
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Solution Overview
Problem
Current integrated circuit (IC) designs face challenges in routing flexibility and latch-up immunity due to limitations in transistor source connections and well strap area utilization, particularly in miniaturized semiconductor structures.
Innovation Solution
The semiconductor structure incorporates buried conductive lines within the isolation structure to electrically connect transistor sources, ensuring the top surface is level with or lower than the isolation structure, thereby enhancing routing flexibility and latch-up immunity while saving well strap area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If transistor sources are connected using conventional routing methods, then routing flexibility is limited, but device complexity is reduced
Solution Approach 1:
The patent embeds conductive lines within the isolation structure (shallow trench isolation), transitioning from surface-level routing to subsurface routing. This dimensional change allows conductive lines to be positioned at different depths, enabling flexible connection of transistor sources without adding lateral complexity to the device layout.
Solution Approach 2:
The conductive lines are nested within the isolation structure, specifically embedded in the shallow trench isolation material. This nesting approach allows the routing infrastructure to be integrated within existing device structures rather than adding separate external routing layers, thereby improving flexibility without proportionally increasing overall device complexity.
2Productivity
If well strap area is reduced to increase logic circuit density, then logic circuit density is improved, but latch-up immunity deteriorates
Solution Approach 1:
The patent moves well connection functionality from the lateral plane (well straps at the surface) to the vertical dimension (conductive lines embedded at depth within isolation structures). This allows well connections to be established without consuming lateral well strap area, thereby maintaining latch-up immunity while increasing logic circuit density.
Solution Approach 2:
The isolation structure serves as an intermediary medium that hosts embedded conductive lines for well connections. Instead of directly using well straps at the surface, the patent uses these subsurface conductive lines as intermediaries to establish well connections, thereby decoupling the well connection function from lateral area consumption.
3Productivity
If conventional routing methods are used, then device structure is simpler, but routing efficiency deteriorates
Solution Approach 1:
The patent implements routing at multiple vertical levels by embedding conductive lines within the isolation structure at controlled depths. This vertical stratification of routing paths allows for more efficient signal routing by providing additional dimensional freedom, improving routing efficiency without requiring excessively complex lateral routing schemes.
Data Source
AI summary
A semiconductor structure is provided. The semiconductor structure includes a first well region over a substrate, and an isolation structure over the first well region. The semiconductor structure also includes a first transistor over the first well region, and a first buried conductive line over the first well region and electrically connected to a source structure of the first transistor. A top surface of the first buried conductive line is substantially level with or lower than a top surface of the isolation structure.