Buried Conductive Lines for Semiconductor Area Reduction
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Solution Overview
Problem
The challenge in semiconductor device manufacturing is to reduce chip size while maintaining efficient electrical connectivity, as existing methods often result in increased chip area due to the layout of power rails and conductive lines.
Innovation Solution
The implementation of buried conductive lines within insulating structures adjacent to transistors allows for reduced chip area by enabling internal electrical connections without occupying additional layout space, achieved through the use of multiple levels of buried conductive lines and careful integration with transistor structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power rails are laid out on the boundaries of standard cells and merged in neighboring rows, then electrical connectivity is improved, but chip area increases
Solution Approach 1:
The patent transitions power rail routing from a two-dimensional planar layout to a three-dimensional structure by forming conductive lines within trenches etched into the substrate. This vertical dimension allows power rails to be embedded below the active device region, enabling electrical connectivity without occupying additional lateral chip area.
Solution Approach 2:
The conductive lines are nested within trenches that are formed in the substrate, effectively embedding the power distribution network inside the chip structure. This nesting approach allows the power rails to coexist with active devices in the same lateral footprint, reducing overall chip area while maintaining connectivity.
2Reliability
If conductive lines are made wider to reduce resistance, then electrical conductivity is improved, but chip area increases
Solution Approach 1:
The patent compensates for reduced conductive line width by increasing the vertical dimension through trench depth. The conductive lines are formed at different depths within the substrate, creating a three-dimensional conduction path that maintains low resistance despite narrower lateral dimensions, thus reducing chip area while preserving electrical conductivity.
3Area of stationary object
If buried conductive lines are formed in trenches, then chip area is reduced, but manufacturing complexity increases
Solution Approach 1:
The manufacturing process is segmented into distinct stages: trench formation, insulation layer deposition, conductive line filling, and planarization. Each stage addresses a specific aspect of the three-dimensional integration, making the complex manufacturing process more manageable and systematic while achieving area reduction.
4Productivity
If power rails are merged in neighboring rows, then power distribution efficiency is improved, but layout flexibility is reduced
Solution Approach 1:
By moving power rail routing to the vertical dimension through trench-based embedding, the patent decouples power distribution from the two-dimensional device layout. This allows independent optimization of power distribution efficiency through trench merging while maintaining layout flexibility for device placement and interconnection in the lateral plane.
Data Source
AI summary
A device includes a transistor, an insulating structure, a buried conductive line, and a buried via. The transistor is above a substrate and includes a source/drain region and a source/drain contact above the source/drain region. The insulating structure is above the substrate and laterally surrounds the transistor. The buried conductive line is in the insulating structure and spaced apart from the transistor. The buried via is in the insulating structure and interconnects the transistor and the buried conductive line. A height of the buried conductive line is greater than a height of the source/drain contact.