Buried Conductive Lines in Vertical Transistor Arrays
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Solution Overview
Problem
In memory arrays, there is a challenge to minimize parasitic capacitance and cross-talk between data/sense lines while maintaining high conductivity, which is crucial for efficient data storage and retrieval in volatile and non-volatile memory cells.
Innovation Solution
The use of vertically-oriented transistors with conductively-doped silicon-comprising semiconductor material for data/sense lines, incorporating a conductivity-neutral dopant to enhance diffusion and reduce resistance, and forming conductive lines buried in silicon-comprising semiconductor material to interconnect transistors, thereby minimizing leakage and cross-talk.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data/sense lines are formed with conventional doping methods, then conductivity can be achieved, but parasitic capacitance and cross-talk between adjacent lines increase
Solution Approach 1:
The patent applies local quality by doping only specific regions of the semiconductor substrate with conductive material. The data/sense lines are formed by doping regions between transistor source/drain regions, while leaving other areas undoped or lightly doped. This localized doping approach provides high conductivity where needed for signal transmission while minimizing parasitic capacitance in adjacent undoped regions, thereby reducing cross-talk between lines.
Solution Approach 2:
The patent transitions from planar doping to vertically-oriented transistor structures with buried conductive lines. The conductive lines are formed at different depth levels within the substrate, creating a three-dimensional arrangement where data/sense lines run beneath the transistor channels. This vertical dimensionality separation reduces parasitic capacitance between adjacent lines by increasing their effective spacing in the depth direction while maintaining compact planar footprint.
2Productivity
If vertically-oriented transistors are used with buried conductive lines, then integration density improves, but manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary action by forming the conductive lines and doping the substrate regions before constructing the vertically-oriented transistor structures. The buried conductive lines are created in the substrate, and subsequent processing steps form the transistor channels, gates, and contacts around these pre-formed lines. This sequence simplifies manufacturing by establishing the conductive interconnect framework early, allowing transistor structures to be built around it using standard vertical processing techniques.
Solution Approach 2:
The patent achieves universality by using the same buried conductive line structures to serve multiple functions: they act as data/sense lines for memory operations, provide electrical interconnection between vertically-oriented transistors, and enable compact three-dimensional integration. The conductively-doped semiconductor regions fulfill both interconnect and transistor channel functions, reducing the need for separate dedicated structures and simplifying the overall manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in reduced parasitic capacitance and cross-talk, improving the signal delivered to sense amplifiers and enhancing the overall performance and integration density of memory arrays.
Implementation Method 1
A conductivity-neutral dopant is provided in the buried volume of silicon-comprising semiconductor material. The conductivity-neutral dopant provides enhanced diffusion of the at least one of As and Sb in the silicon-comprising semiconductor material than would otherwise occur under a set of heating conditions
Implementation Method 2
The buried volume of silicon-comprising semiconductor material is subjected to the set of heating conditions to cause the laterally-spaced n-type regions to interconnect
Data Source
AI summary
An array includes vertically-oriented transistors, rows of access lines, and columns of data/sense lines. Individual of the rows include an access line interconnecting transistors in that row. Individual of the columns include a data/sense line interconnecting transistors in that column. The data/sense line has silicon-comprising semiconductor material between the transistors in that column that is conductively-doped n-type with at least one of As and Sb. The conductively-doped semiconductor material of the data/sense line includes a conductivity-neutral dopant between the transistors in that column. Methods are disclosed.