Buried Conductive Structure With Metal Capping for Low Resistance

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Solution Overview

Problem

The increasing demand for higher storage capacity, faster processing, and lower costs in semiconductor technology has led to challenges in reducing the resistance of buried conductive structures in semiconductor devices, which affects device performance.

Innovation Solution

The formation of metal capping layers below the bottom silicide layers using an atomic layer deposition (ALD) or chemical vapor deposition (CVD) process prevents oxidation and maintains the thickness of the bottom silicide layers, thereby reducing the resistance of buried conductive structures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional fabrication processes are used without metal capping layers, then the process is simpler, but the bottom silicide layers oxidize and resistance increases

Engineering Contradiction:
Improveresistance of buried conductive structuresVSAvoidfabrication process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Metal capping layers are formed on the bottom silicide layers before subsequent fabrication steps to prevent oxidation. This preliminary protective action ensures the silicide layers maintain their low-resistance properties throughout the fabrication process, resolving the contradiction between reliability and process complexity.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The metal capping layer acts as an intermediary protective barrier between the bottom silicide layer and the oxidizing environment. This intermediary layer prevents direct contact between oxygen and the silicide, maintaining electrical conductivity while allowing the fabrication process to proceed.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If metal capping layers are formed using ALD or CVD processes, then oxidation is prevented and resistance is reduced, but the manufacturing process becomes more complex

Engineering Contradiction:
Improveresistance of buried conductive structuresVSAvoidease of forming metal capping layers
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent specifies particular thickness ranges for the metal capping layers (e.g., 1-10 nm) and uses established ALD/CVD processes with controlled parameters. By optimizing these parameters, the patent achieves effective oxidation protection with minimal impact on manufacturing ease, balancing reliability improvements with manufacturing considerations.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach results in low resistance buried conductive structures, enhancing the performance of semiconductor devices by maintaining the thickness of the bottom silicide layers and preventing oxidation.

Implementation Method 1

The formation of metal capping layers below the bottom silicide layers using an atomic layer deposition (ALD) or chemical vapor deposition (CVD) process prevents oxidation

Methodology Applied
Scientific EffectAtomic layer deposition: Deposition (physical)

Implementation Method 2

The formation of metal capping layers below the bottom silicide layers using an atomic layer deposition (ALD) or chemical vapor deposition (CVD) process prevents oxidation

Methodology Applied
Scientific EffectChemical vapor deposition: Chemical Vapour Deposition

Data Source

PatentUS12272621B2Buried conductive structure in semiconductor substrate
Publication Date: 2025.04.08 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12272621B2 patent drawing
  • US12272621B2 patent drawing
  • US12272621B2 patent drawing

AI summary

The present disclosure describes a buried conductive structure in a semiconductor substrate and a method for forming the structure. The structure includes an epitaxial region disposed on a substrate and adjacent to a nanostructured gate layer and a nanostructured channel layer, a first silicide layer disposed within a top portion of the epitaxial region, and a first conductive structure disposed on a top surface of the first silicide layer. The structure further includes a second silicide layer disposed within a bottom portion of the epitaxial region and a second conductive structure disposed on a bottom surface of the second silicide layer and traversing through the substrate, where the second conductive structure includes a first metal layer in contact with the second silicide layer and a second metal layer in contact with the first metal layer.