Buried Conductive Structure With Silicide Capping Against Plasma Thinning

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Solution Overview

Problem

The reduction in size of interconnect structures in semiconductor devices leads to increased resistance due to the conversion and removal of bottom silicide layers during nitrogen-based plasma processes, affecting the performance of semiconductor devices.

Innovation Solution

Formation of metal capping layers below the bottom silicide layers using atomic layer deposition (ALD) or chemical vapor deposition (CVD) processes to prevent oxidation and maintain the thickness of the silicide layers, accompanied by the formation of buried conductive structure liners and metal fill layers without plasma bombardment.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If nitrogen-based plasma processes are used to convert and remove bottom silicide layers, then interconnect structures can be formed, but the thickness of silicide layers is reduced and resistance increases

Engineering Contradiction:
Improveinterconnect structure formationVSAvoidsilicide layer thickness
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

A metal capping layer is formed on the bottom silicide layer before the nitrogen-based plasma process. This preliminary protective action prevents the plasma from removing the silicide layer, thereby maintaining its thickness while still allowing the interconnect formation process to proceed

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The metal capping layer acts as an intermediary between the nitrogen-based plasma and the bottom silicide layer. It absorbs the harmful effect of the plasma (preventing silicide removal) while allowing the plasma process to continue for interconnect formation

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of manufacture

If nitrogen-based plasma processes are used to convert and remove bottom silicide layers, then interconnect structures can be formed, but resistance of buried conductive structures increases

Engineering Contradiction:
Improveinterconnect structure formationVSAvoidelectrical coupling efficiency
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The metal capping layer is deposited beforehand to protect the bottom silicide layer from plasma-induced thinning. This preliminary protection ensures that the silicide layer maintains its original thickness, thereby preserving low resistance and high electrical coupling efficiency in the buried conductive structures

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The metal capping layer, which might seem like an added complexity, actually converts the harmful plasma bombardment into a beneficial protective mechanism. It allows the plasma process to proceed for interconnect formation while preventing the harmful removal of silicide material, thus maintaining electrical performance

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The retained thickness of the silicide layers reduces the resistance of the buried conductive structures, enhancing the performance of semiconductor devices by maintaining electrical coupling efficiency.

Implementation Method 1

metal capping layers below the bottom silicide layers using atomic layer deposition (ALD) or chemical vapor deposition (CVD) processes to prevent oxidation

Methodology Applied
Scientific EffectOxidation prevention: Oxidation

Implementation Method 2

Formation of metal capping layers below the bottom silicide layers using atomic layer deposition (ALD)

Methodology Applied
Scientific EffectAtomic layer deposition: Deposition (physical)

Implementation Method 3

Formation of metal capping layers below the bottom silicide layers using atomic layer deposition (ALD) or chemical vapor deposition (CVD) processes

Methodology Applied
Scientific EffectChemical vapor deposition: Chemical Vapour Deposition

Data Source

PatentUS20250226291A1Buried conductive structure in semiconductor substrate
Publication Date: 2025.07.10 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250226291A1 patent drawing
  • US20250226291A1 patent drawing
  • US20250226291A1 patent drawing

AI summary

The present disclosure describes a buried conductive structure in a semiconductor substrate and a method for forming the structure. The structure includes an epitaxial region disposed on a substrate and adjacent to a nanostructured gate layer and a nanostructured channel layer, a first silicide layer disposed within a top portion of the epitaxial region, and a first conductive structure disposed on a top surface of the first silicide layer. The structure further includes a second silicide layer disposed within a bottom portion of the epitaxial region and a second conductive structure disposed on a bottom surface of the second silicide layer and traversing through the substrate, where the second conductive structure includes a first metal layer in contact with the second silicide layer and a second metal layer in contact with the first metal layer.