Buried Contact SRAM Cell for Sub-10nm FinFET Integration
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Solution Overview
Problem
Current SRAM technologies face challenges in integrating more data storage cells and reducing power consumption, particularly when shrinking FinFET pitch below 10 nm, due to issues with insufficient overlay budget and potential short-circuits caused by conventional contact methods.
Innovation Solution
The implementation of buried contacts in SRAM cells, which connect metal contacts and gate electrodes through a doped semiconductor region and metal layer formed in a region confined by spacers of the gate layer, providing an electrically conductive path below the spacers, replaces traditional butted contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional butted contacts are used to connect metal contacts and gate electrodes, then the manufacturing process is simpler, but insufficient overlay budget and potential short-circuits occur when shrinking FinFET pitch below 10 nm
Solution Approach 1:
The patent transitions from a planar contact structure to a three-dimensional buried contact structure. The conductive path is formed by extending the contact region vertically below the gate electrode level, utilizing the depth dimension to achieve electrical connection without requiring precise lateral alignment. This dimensional change resolves the overlay budget issue by eliminating the need for precise horizontal positioning between metal contacts and gate electrodes.
Solution Approach 2:
The patent introduces a doped semiconductor region as an intermediary conductive path between the metal contact and the gate electrode. This intermediary buried contact region, formed by lateral extension of the contact, provides a reliable electrical connection without requiring direct contact between the metal contact and gate electrode, thus avoiding short-circuit risks while maintaining electrical functionality.
2Productivity
If FinFET pitch is shrunk below 10 nm to increase integration density, then more data storage cells can be integrated, but overlay budget becomes insufficient and short-circuits may occur
Solution Approach 1:
By utilizing the vertical dimension below the gate electrode level, the patent enables electrical connections without requiring precise lateral alignment at the surface level. The buried contact structure extends downward, allowing pitch scaling below 10 nm while maintaining sufficient overlay budget for manufacturing.
Solution Approach 2:
The doped semiconductor buried contact acts as an intermediary that provides electrical connection between separated elements. This mediator approach allows pitch reduction by decoupling the lateral positioning requirements, enabling higher integration density without compromising manufacturing precision.
3Reliability
If conventional contact methods are used, then the device structure is simpler, but potential short-circuits occur when scaling to smaller pitches
Solution Approach 1:
The patent introduces a doped semiconductor buried contact as an intermediary element between the metal contact and gate electrode. This intermediary structure provides reliable electrical connection while physically separating the metal contact from the gate electrode, eliminating short-circuit risks. The added complexity is localized to the contact region and enables robust electrical connections for scaled devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively avoids the limitations of insufficient overlay budget and potential short-circuits, enabling higher density integration and reduced power consumption in SRAM cells by ensuring reliable electrical connections.
Implementation Method 1
connect metal contacts and gate electrodes to each other and to the doped semiconductor region, which serves as an additional buried contact
Data Source
AI summary
A Static Random Access Memory (SRAM) cell includes a first pull-up transistor and a first pull-down transistor, a second pull-up transistor and a second pull-down transistor, and first and second pass-gate transistors. A first buried contact electrically connects a drain region of the first pull-up transistor and gate electrodes of the second pull-up transistor and the second pull-down transistor, and includes a first metal layer formed in a region confined by spacers of a first gate layer and a first electrically conductive path formed at a level below the spacers. A second buried contact electrically connects a drain region of the second pull-up transistor and gate electrodes of the first pull-up transistor and the first pull-down transistor, and includes a second metal layer formed in a region confined by spacers of a second gate layer and a second electrically conductive path formed at the level below the spacers.