Buried Decoupling Capacitors in SOI Substrates
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Solution Overview
Problem
Integrated circuit design faces challenges in achieving smaller feature sizes and faster clock frequencies due to increasing voltage droop and inductive noise, which are exacerbated by the use of traditional decoupling capacitors that occupy large chip areas and impact cost and performance.
Innovation Solution
The implementation of buried decoupling capacitors using a semiconductor-on-insulator substrate with a buried insulator region and a dielectric material between capacitor plates, reducing the need for excessive chip area and topography while maintaining performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If traditional decoupling capacitors are used, then electrical noise and voltage droops are reduced, but chip area and topography increase
Solution Approach 1:
The patent merges the decoupling capacitor structure with the semiconductor-on-insulator substrate by using the buried insulator region as part of the capacitor structure. The capacitor plates are formed within the substrate layers rather than as separate on-chip components, effectively combining the substrate and decoupling capacitor into a single integrated structure. This eliminates the need for additional chip area dedicated to decoupling capacitors while maintaining their noise-reduction function.
Solution Approach 2:
The patent embeds the decoupling capacitor plates within the existing substrate layers. The first capacitor plate is formed in the semiconductor layer and the second capacitor plate is formed in the buried insulator region, nesting the capacitor structure within the substrate itself. This nested arrangement allows the decoupling function to be achieved without occupying additional chip area, as the capacitor is hidden within the existing structure.
2Object-affected harmful factors
If traditional decoupling capacitors are used, then electrical noise and voltage droops are reduced, but chip cost increases
Solution Approach 1:
By combining the decoupling capacitor function with the substrate structure, the patent eliminates the need for separate capacitor fabrication processes and additional material layers. The capacitor plates are formed using the existing semiconductor and insulator layers of the SOI substrate, reducing manufacturing steps and material costs while maintaining the voltage droop compensation function.
3Area of stationary object
If capacitor layers are stacked to reduce area, then chip area is reduced, but topography and manufacturing complexity increase
Solution Approach 1:
The patent nests the capacitor plates within the substrate layers rather than stacking them vertically on the chip surface. The first plate is in the semiconductor layer and the second plate is in the buried insulator region, creating a planar structure that does not add topography. This nested arrangement within the substrate thickness avoids the topography issues associated with vertical stacking on the chip surface.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces electrical noise and voltage droops without increasing chip area or topography, thereby enhancing performance and decreasing production costs.
Implementation Method 1
a dielectric material between capacitor plates
Implementation Method 2
a dielectric material between capacitor plates
Data Source
AI summary
A buried decoupling capacitor apparatus and method are provided. According to various embodiments, a buried decoupling capacitor apparatus includes a semiconductor-on-insulator substrate having a buried insulator region and top semiconductor region on the buried insulator region. The apparatus embodiment also includes a first capacitor plate having a doped region in the top semiconductor region in the semiconductor-on-insulator substrate. The apparatus embodiment further includes a dielectric material on the first capacitor plate, and a second capacitor plate on the dielectric material. According to various embodiments, the first capacitor plate, the dielectric material and the second capacitor plate form a decoupling capacitor for use in an integrated circuit.