Buried Die Interconnect Layout for Edge Contacts Without TSV Stress
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Solution Overview
Problem
Conventional approaches for providing external contacts to semiconductor devices using through-substrate vias cause mechanical stresses and increase manufacturing costs due to the need for design rules to avoid sensitive devices, leading to increased die footprints.
Innovation Solution
The use of buried electrical interconnects that run parallel to the upper and lower surfaces of a semiconductor die, reducing the need for interconnections through the substrate and allowing edge contacts, which are formed using conductive materials like tungsten, copper, or nickel, and surrounded by dielectric material to isolate them from the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-substrate vias are used for external contacts, then electrical connections can be established, but mechanical stresses are caused on sensitive devices
Solution Approach 1:
The patent transitions from vertical through-substrate vias to lateral buried interconnects that extend horizontally from the device region toward the die edge. This dimensional change eliminates the need for vertical penetration through the substrate, thereby avoiding mechanical stress on sensitive devices while maintaining electrical connectivity.
2Reliability
If through-substrate vias are used for external contacts, then electrical connections can be established, but manufacturing costs increase due to design rules
Solution Approach 1:
By routing interconnects laterally within the substrate rather than vertically through it, the patent eliminates the need for complex via formation processes and associated design rules, thereby reducing manufacturing complexity and cost.
3Reliability
If through-substrate vias are used, then external contacts are provided, but die footprint increases
Solution Approach 1:
The lateral extension of buried interconnects toward the die edge utilizes the horizontal space within the substrate volume, avoiding the need for additional vertical layers and associated footprint expansion that would result from through-substrate via structures.
4Object-affected harmful factors
If buried interconnects are used, then mechanical stresses are reduced, but additional manufacturing steps are required
Solution Approach 1:
The patent integrates the formation of buried interconnects with existing substrate preparation and device fabrication steps. By combining the interconnect formation with standard manufacturing flows rather than adding completely separate processes, the increase in manufacturing complexity is minimized while achieving mechanical stress reduction.
Data Source
AI summary
One or more electrical interconnects are formed beneath a device region within a volume of semiconductor material in which electronic devices are formed. The buried interconnects extended in a lateral direction parallel to surfaces of the die toward an edge of the semiconductor die. Such buried interconnects can be exposed at edges of the die to provide electrical contacts along those edges and can be coupled to electronic devices formed within the device region as alternatives to or in addition to contacts formed on top or bottom surfaces of the die.