Buried Digit Line Memory Cell Layout for Density and Noise Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Integrated circuit designers face challenges in increasing the density and performance of memory devices like DRAM cells while minimizing pattern noise and electrical performance degradation due to reduced feature sizes and separation distances between memory elements and connecting lines.
Innovation Solution
The use of double gate field effect transistors (FETs) coupled with a capacitor storage device, where both word lines are tied together to reduce effective resistance and increase access speed, along with a finFET structure that allows for compact and efficient fabrication of memory cells with a 4F2 cell size, utilizing a buried digit line and optimized trench isolation to minimize coupling capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If feature sizes and separation distances are reduced to increase density, then integration density is improved, but pattern noise increases and electrical performance decreases
Solution Approach 1:
The patent transitions from planar digit lines to vertically-oriented buried digit lines extending beneath memory cell rows. This dimensional change allows digit lines to pass under multiple word lines without horizontal interference, reducing pattern noise while maintaining high density through vertical stacking rather than horizontal expansion.
Solution Approach 2:
The patent segments the digit line into multiple buried digit line portions positioned at different vertical levels beneath different rows of memory cells. Each segment is electrically isolated by insulating layers, allowing independent routing that minimizes capacitive coupling and pattern noise between adjacent signal paths.
2Quantity of substance
If feature sizes are reduced to increase density, then integration density is improved, but electrical performance decreases
Solution Approach 1:
By moving digit lines to a vertical dimension beneath memory cell rows rather than horizontal placement, the patent reduces parasitic capacitance between digit lines and word lines. This dimensional reconfiguration maintains signal integrity and electrical performance while enabling higher integration density through vertical space utilization.
Solution Approach 2:
The patent introduces insulating layers as intermediary structures between buried digit lines and memory cell components. These intermediary layers electrically isolate the digit lines from capacitive coupling with word lines and memory cell plates, preserving electrical performance despite reduced feature sizes and increased density.
3Ease of operation
If digit lines are positioned horizontally adjacent to memory cells, then connectivity is simplified, but capacitive coupling increases and performance decreases
Solution Approach 1:
The patent repositions digit lines from horizontal adjacency to vertical burial beneath memory cell rows. This dimensional change maintains connectivity to all memory cells in a column while eliminating horizontal capacitive coupling with word lines, thereby improving performance without sacrificing connectivity.
Solution Approach 2:
Insulating layers serve as intermediaries between the buried digit lines and the underlying memory cell structures. These intermediaries provide electrical isolation that reduces unwanted capacitive coupling while allowing the digit lines to maintain functional connectivity to memory cell data lines through vertical alignment and contact structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the speed and efficiency of memory access, reduces pattern noise, and maintains performance by effectively reducing the resistance and optimizing the layout of memory cells within a compact array structure.
Implementation Method 1
a first buried digit line extending beneath a first plurality of memory cells in a first direction, a second buried digit line extending beneath a second plurality of memory cells in the first direction
Implementation Method 2
optimized trench isolation to minimize coupling capacitance
Implementation Method 3
double gate field effect transistors (FETs) coupled with a capacitor storage device
Data Source
AI summary
A memory array having memory cells and methods of forming the same. The memory array may have a buried digit line formed in a first horizontal planar volume, a word line formed in a second horizontal planar volume above the first horizontal planar volume and storage devices formed on top of the vertical access devices, such as finFETs, in a third horizontal planar volume above the second horizontal planar volume. The memory array may have a 4F2 architecture, wherein each memory cell includes two vertical access devices, each coupled to a single storage device.