Buried Digit Line Resistance in Semiconductor Pillar Structures
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Solution Overview
Problem
As the packing density in integrated circuits increases, it becomes challenging to reduce the resistance of buried digit lines in semiconductor memory arrays, necessitating an improved memory structure and fabrication method.
Innovation Solution
A semiconductor structure with deep trenches and pillar structures, where a doping region is formed in the lower portion of the pillars, and a diffusion barrier layer is deposited on the sidewalls to minimize dopant loss and achieve low-resistance buried digit lines, using techniques like gap phase diffusion and atomic layer deposition for the diffusion barrier layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If packing density in integrated circuits is increased, then memory array integration is improved, but resistance of buried digit lines increases
Solution Approach 1:
The patent applies local quality by creating a doping region specifically in the lower portion of the pillar structure where the buried digit line is formed. This localized doping concentrates dopants in the critical region to reduce resistance without requiring uniform doping throughout the entire structure, thus maintaining low resistance even as packing density increases.
Solution Approach 2:
The patent implements nesting by placing the buried digit line within the pillar structure. The pillar structure contains the doping region and diffusion barrier layer, which in turn contain the buried digit line. This nested arrangement allows the digit line to be embedded within existing structural elements, reducing the need for additional space and maintaining low resistance in densely packed arrays.
2Reliability
If doping is performed to reduce buried digit line resistance, then electrical conductivity is improved, but dopant diffusion loss increases
Solution Approach 1:
The patent applies preliminary action by forming the diffusion barrier layer on the sidewall of the pillar structure before performing the doping process. This pre-formed barrier prevents dopant diffusion loss during subsequent thermal processing steps, ensuring that dopants remain concentrated in the desired region and maintain electrical conductivity without excessive diffusion.
Solution Approach 2:
The diffusion barrier layer acts as an intermediary between the doping region and the surrounding semiconductor material. It mediates the doping process by selectively blocking dopant diffusion in certain directions while allowing doping in the desired region, thus reducing dopant loss and maintaining precise dopant placement for optimal conductivity.
3Ease of manufacture
If conventional doping methods are used, then manufacturing simplicity is maintained, but dopant diffusion control is insufficient
Solution Approach 1:
The patent introduces a diffusion barrier layer as an intermediary component that enables precise dopant diffusion control. This barrier layer can be formed using standard deposition techniques, maintaining manufacturing simplicity while providing the precision needed to control dopant diffusion boundaries and achieve the desired doping profile in the buried digit line region.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces the resistance of buried digit lines, maintaining dopant integrity and enabling efficient electrical interconnection in densely packed memory arrays.
Implementation Method 1
A diffusion barrier layer is disposed on a sidewall of the lower portion. The diffusion barrier layer is in direct contact with the sidewall of the lower portion.
Implementation Method 2
A doping region is formed in the lower portion
Data Source
AI summary
A semiconductor structure includes a semiconductor substrate having thereon a plurality of deep trenches and a plurality of pillar structures between the deep trenches, wherein each of the plurality of pillar structures comprises an upper portion and a lower portion. A doping region is formed in the lower portion. A diffusion barrier layer is disposed on a sidewall of the lower portion.