Buried Digit Line Formation Using Self-Aligned Spacing Layer
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Solution Overview
Problem
Conventional digit line structures in semiconductor devices require high aspect ratio openings, leading to difficulties in achieving complete metal fill and high electrical resistance, and the use of discrete spacers increases lateral space and mask misalignment issues.
Innovation Solution
A method for forming a buried digit line using a single precision mask, reducing the need for discrete spacers, where a planarized dielectric layer is etched selective to the semiconductor wafer, and a tungsten layer is deposited and planarized to create damascene features, allowing for reduced aspect ratios and improved electrical isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional digit line is formed at a level above the storage capacitor, then the digit line can contact the doped region directly, but the opening requires a severe aspect ratio (10:1 or more) which is difficult to achieve and may leave voids and high electrical resistance
Solution Approach 1:
The patent transitions from a vertical contact approach (above the capacitor) to a horizontal/buried approach (below the capacitor). The digit line is formed in a lower dielectric layer, changing the spatial dimension of contact and eliminating the need for deep vertical openings through the capacitor structure.
Solution Approach 2:
The digit line is formed preliminarily before the capacitor structure is completed. By forming the digit line in a lower dielectric layer first, the patent avoids the need to create high aspect ratio openings through the finished capacitor, as the contact path is established in advance in a more accessible layer.
2Reliability
If discrete spacers are used to prevent contact between the buried digit line and other conductive features, then electrical isolation is achieved, but lateral space is increased and mask misalignment issues arise
Solution Approach 1:
The patent merges the spacer function into the self-aligned spacing layer that is formed concurrently with the digit line contact plug. Instead of adding discrete spacers as separate components, the spacing function is integrated into the same structural layer, eliminating additional lateral space requirements and mask alignment steps.
Solution Approach 2:
The spacing layer is self-aligned, meaning it automatically positions itself relative to the digit line and other features without requiring additional masking and alignment operations. The layer serves both as a spacer and as a structural component, eliminating the need for separate spacer formation steps.
3Device complexity
If the number of critical masking patterns is reduced to a single precision mask, then manufacturing complexity is decreased, but the precision required for that single mask increases
Solution Approach 1:
The self-aligned spacing layer performs the alignment function automatically, eliminating the need for multiple precision masks. The spacing layer's inherent alignment properties allow a single mask to define both the digit line contact plug and the spacing features without requiring additional alignment operations.
Solution Approach 2:
The single precision mask serves multiple functions: defining the digit line contact plug, establishing the spacing layer pattern, and ensuring proper alignment with other features. The self-aligned spacing layer enables this multi-functionality by providing automatic alignment for all features defined by the single mask.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the number of critical masking patterns, minimizes lateral space usage, and enhances the reliability of semiconductor devices by eliminating the need for discrete spacers, thereby improving the aspect ratio and electrical properties of the digit line.
Implementation Method 1
a planarized dielectric layer is etched selective to the semiconductor wafer
Implementation Method 2
a tungsten layer is deposited and planarized to create damascene features
Data Source
AI summary
A method for use during fabrication of a semiconductor device comprises the formation of buried digit lines and contacts. During formation, a buried bit line layer may be used as a mask to etch one or more openings in a dielectric layer. A conductive layer is then formed in the one or more openings in the dielectric layer, and is then planarized to form one or more individual contact plugs. Next, the buried bit line layer is etched to recess the buried bit line layer, and a capacitor plate is formed to contact the contact plug.