Buried Double-Bit Line Layout for Vertical Channel Memory Arrays
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Solution Overview
Problem
The wiring layout and technological process for semiconductor devices with vertical channel structures need optimization to improve integration level and reduce parasitic capacitance between bit lines.
Innovation Solution
A manufacturing method involving the formation of first and second trenches with different depths on a substrate, deposition of conductive layers in gaps between isolation layers and sidewalls to form parallel bit lines, and integration of word lines within these trenches, creating a double-bit line structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If vertical channel structures are used to improve integration level, then substrate utilization improves, but wiring layout complexity increases
Solution Approach 1:
The patent transitions from planar wiring to three-dimensional wiring by forming bit lines at different depths within trenches. The first bit line is formed at a first depth and the second bit line at a second depth greater than the first depth, creating a vertical stacking arrangement that resolves wiring layout complexity while maintaining high integration.
Solution Approach 2:
The patent divides the wiring structure into segmented bit lines positioned at different depths. The first bit line and second bit line are separated vertically within the trench structure, allowing independent routing and reducing wiring complexity while improving integration density.
2Ease of manufacture
If conventional single bit line structure is used, then manufacturing is simpler, but parasitic capacitance between bit lines is higher
Solution Approach 1:
The patent reduces parasitic capacitance by separating bit lines in the vertical dimension rather than only horizontal spacing. The first bit line at first depth and second bit line at second depth create greater physical separation, reducing capacitive coupling while maintaining manufacturability through trench-based formation.
Solution Approach 2:
The patent introduces an isolation layer as an intermediary between the first bit line and second bit line. This isolation layer, positioned between the bit lines at different depths, acts as a dielectric barrier that reduces parasitic capacitance while allowing the bit lines to be formed in the same trench structure.
3Ease of manufacture
If bit lines are formed at the same depth, then manufacturing is easier, but conductivity and integration level are limited
Solution Approach 1:
The patent forms bit lines at different vertical depths (first depth and second depth) within trenches to enhance conductivity. This vertical arrangement allows for optimized electrical pathways and improved signal transmission while maintaining ease of manufacture through a unified trench formation process followed by selective filling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances conductivity and integration level while reducing parasitic capacitance by forming buried bit lines with a parallel double-bit line structure, improving overall semiconductor device performance.
Implementation Method 1
depositing conductive layers of a first conductive material at bottoms of the first gaps on both sides of the first trench
Data Source
AI summary
A semiconductor device and a manufacturing method thereof are provided. The method includes: forming a plurality of first trenches extending in a first direction on the substrate; forming a plurality of second trenches extending in a second direction on the substrate; forming a first isolation layer in at least one of the first trenches and at least one of the second trenches, first gaps are respectively provided between the first isolation layer and sidewalls on both sides of the first trench; forming two bit lines which are parallel to each other and extend in the first direction by depositing conductive layers of a first conductive material at bottoms of the first gaps on both sides of the first trench; and forming word lines extending in the second direction in the first trench and the second trench, and above the conductive layers in the first trench.