Buried Edge Dielectric Structure for Crack-Resistant Semiconductor Chips
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Solution Overview
Problem
Existing semiconductor chip fabrication methods face challenges in preventing physical cracks and moisture absorption at the edge regions, which can lead to reduced reliability and increased defects during the dicing process.
Innovation Solution
The implementation of a semiconductor chip design that includes a substrate with a device region and edge region, featuring a wiring layer with a separation dielectric pattern and a buried dielectric pattern, along with a capping layer and passivation layers to create a stepped region, which helps prevent physical cracks and moisture absorption by using materials with varying dielectric constants and densities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional semiconductor chip structure without buried dielectric pattern is used, then the manufacturing process is simpler, but physical cracks and moisture absorption occur at edge regions during dicing
Solution Approach 1:
The buried dielectric pattern is formed in advance at the edge region before the dicing process. This preliminary structural preparation creates a protective barrier that prevents physical cracks and moisture absorption during subsequent manufacturing steps, thereby improving chip reliability without requiring fundamental changes to the overall manufacturing flow
Solution Approach 2:
The buried dielectric pattern is specifically placed only at the edge region of the semiconductor chip, not throughout the entire structure. This localized approach provides targeted protection against cracks and moisture at the vulnerable edge areas while maintaining simpler structures in the device regions, thus improving reliability without excessive complexity
2Reliability
If the first capping layer and buried dielectric pattern are formed with the same density, then the manufacturing process is simpler, but physical cracks occur during dicing due to uniform stress distribution
Solution Approach 1:
The density of the first capping layer is specifically controlled to be greater than the density of the buried dielectric pattern. This parameter change creates a density gradient that results in differential stress distribution, with the denser capping layer providing compressive stress that counteracts tensile stresses during dicing, thereby preventing crack formation
Solution Approach 2:
Different density values are assigned to different layers (first capping layer versus buried dielectric pattern) based on their specific functional requirements. The capping layer uses higher density for crack resistance, while the buried dielectric pattern uses lower density for stress management, creating locally optimized properties that prevent cracking
3Reliability
If the edge region is left without additional protective structures, then the manufacturing process is simpler, but moisture absorption occurs during storage and operation
Solution Approach 1:
The buried dielectric pattern is formed in advance at the edge region to create a moisture barrier before the chip is exposed to storage or operating environments. This preliminary protective structure prevents moisture ingress at the vulnerable edge areas, improving moisture resistance without requiring complex post-processing or additional protective coatings
Solution Approach 2:
The protective structure is segmented into two distinct components: the first capping layer covering the top surface and the buried dielectric pattern at the edge region. This segmentation allows each component to perform its specific function - the capping layer provides surface protection while the buried dielectric pattern provides edge sealing - achieving comprehensive moisture resistance through divided functional elements
Data Source
AI summary
A semiconductor chip, a semiconductor package including the same, and a method of fabricating the same, the semiconductor chip including a substrate that includes a device region and an edge region; a device layer and a wiring layer that are sequentially stacked on the substrate; a subsidiary pattern on the wiring layer on the edge region; a first capping layer that covers a sidewall of the subsidiary pattern, a top surface of the wiring layer, and a sidewall of the wiring layer, the first capping layer including an upper outer sidewall and a lower outer sidewall, the lower outer sidewall being offset from the upper outer sidewall; and a buried dielectric pattern in contact with the lower outer sidewall of the first capping layer and spaced apart from the upper outer sidewall of the first capping layer.