Buried Electrode Layout in Stacked Imaging Elements for Smaller Pixels
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Solution Overview
Problem
Conventional imaging elements face challenges in downsizing due to the need for separate substrates for pixel circuits and reference potential connections, which increase pixel area.
Innovation Solution
The proposed imaging element incorporates a first semiconductor substrate with photoelectric conversion, charge holding, and transfer sections, a second substrate with a pixel circuit, and an isolating section, along with buried electrodes to reduce substrate connections and area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If circuits are divided into two substrates and stacked, then manufacturing flexibility and circuit performance are improved, but pixel area increases due to required connection regions
Solution Approach 1:
The patent moves the reference potential connection from a planar surface connection to a subsurface/buried connection. The connection location is positioned beneath the pixel surface, utilizing the vertical dimension and subsurface space to establish electrical connection between substrates without occupying pixel area on the surface plane.
Solution Approach 2:
The patent introduces a connection location as an intermediary structure that facilitates reference potential connection between the first and second substrates. This intermediary connection mechanism allows electrical connection without requiring surface area, as the connection occurs through the substrate thickness rather than across the pixel surface.
2Reliability
If reference potential connection is made between substrates, then electrical reference is established, but pixel area increases due to connection region requirements
Solution Approach 1:
The reference potential connection is relocated from the pixel surface to the subsurface region. By utilizing the vertical dimension and embedding the connection location within the substrate structure, the patent establishes reliable electrical reference connection without consuming pixel area on the surface plane.
Solution Approach 2:
The connection location serves as an intermediary structure that provides the reference potential connection pathway between substrates. This intermediary mechanism ensures reliable electrical reference while occupying minimal to zero pixel surface area, as the connection occurs through rather than across the pixel surface.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for a more compact imaging element design by minimizing the area required for substrate connections, enabling smaller pixel sizes and improved efficiency.
Implementation Method 1
a photoelectric conversion section that performs photoelectric conversion of incident light
Data Source
AI summary
To downsize an imaging element formed by stacking a plurality of semiconductor substrates. The imaging element includes pixels, a pixel circuit, an isolating section, a buried electrode, and a connecting location. Each of the pixels includes: a photoelectric conversion section on the first semiconductor substrate; a charge holding section that holds a charge generated by the photoelectric conversion section; and a charge transfer section. The pixel circuit generates an image signal on the basis of charges disposed and held on a second semiconductor substrate stacked on the front surface side of the first semiconductor substrate. The isolating section is disposed at a boundary of the pixels. The buried electrode is disposed at the boundary of the pixel overlapping the isolating section, so as to be connected to the first semiconductor substrate. The connecting location is connected to the buried electrode.