Buried Epitaxy Strap With Airgap for Lower Parasitic Capacitance
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Solution Overview
Problem
Conventional semiconductor devices experience high parasitic capacitance between contact trenches and gates, which slows down circuit operation due to the formation of interconnections within the contact trench or metallization layers, restricting the use of smaller critical dimensions and thermal budgets.
Innovation Solution
A method involving the formation of p-type and n-type epitaxial regions with an airgap between them, followed by the deposition of dielectrics and selective etching to create a strapped contact, allowing for a metallization layer to be applied, thereby reducing parasitic capacitance and eliminating the need for contacts at MOL or M1 levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If interconnections are formed within the contact trench or at metallization layers, then local interconnect between neighboring n-FETs and p-FETs is achieved, but parasitic capacitance increases
Solution Approach 1:
The patent extracts the interconnect function from the conventional contact trench location and relocates it to a buried position between the source and drain regions. The strapped silicide is formed in a trench that is filled and buried, removing the interconnect from the visible contact area and reducing its capacitive coupling to the gate.
Solution Approach 2:
The patent transitions the interconnect from a planar location at the metallization layer to a three-dimensional buried position between the source and drain epitaxial regions. This spatial repositioning in the vertical dimension allows the interconnect to be hidden beneath the active device regions, reducing parasitic capacitance while maintaining electrical connectivity.
2Ease of manufacture
If contact trenches are used for interconnections, then local interconnect is achieved, but circuit operation speed decreases
Solution Approach 1:
The patent extracts the interconnect from the contact trench position and relocates it to a buried strapped silicide structure. This removal of the interconnect from the capacitive coupling path between the contact and gate reduces the parasitic capacitance that slows down circuit operation.
3Speed
If parasitic capacitance is reduced by burying the strapped contact, then circuit operation speed improves, but device structure complexity increases
Solution Approach 1:
The patent merges the formation of the buried strapped contact with the existing source and drain epitaxial region formation processes. The strapped silicide is formed in a trench that is subsequently filled with dielectric material and planarized, integrating the buried interconnect formation into the standard CMOS fabrication sequence without requiring entirely separate process modules.
4Device complexity
If conventional interconnect formation is used, then manufacturing process is simple, but parasitic capacitance between TS and gate increases
Solution Approach 1:
The patent relocates the interconnect from the planar metallization layer to a three-dimensional buried position between the source and drain regions. This spatial repositioning reduces the overlap area between the interconnect and the gate, thereby reducing parasitic capacitance while maintaining manufacturability through adapted fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces parasitic capacitance, allows for smaller device dimensions, and provides an additional area gain at the MOL and M1 levels by burying the strapping contact and maintaining an airgap between the epitaxial regions, enhancing circuit performance.
Implementation Method 1
The excess parasitic capacitance between the TS and the gate is undesirable because it can slow down the circuit operation
Implementation Method 2
depositing a first dielectric between the p-type epitaxial region and the n-type epitaxial region such that an airgap is defined therebetween
Implementation Method 3
forming a p-type epitaxial region and an n-type epitaxial region over a substrate, depositing an epitaxial growth over the p-type epitaxial region and the n-type epitaxial region
Data Source
AI summary
A method is presented for reducing parasitic capacitance. The method includes forming a p-type epitaxial region and an n-type epitaxial region over a substrate, depositing an epitaxial growth over the p-type epitaxial region and the n-type epitaxial region, depositing a first dielectric between the p-type epitaxial region and the n-type epitaxial region such that an airgap is defined therebetween, and selectively removing the epitaxial growth to expose top surfaces of the p-type and n-type epitaxial regions. The method further includes depositing a second dielectric in direct contact with the exposed top surfaces of the p-type and n-type epitaxial regions, selectively etching the first and second dielectrics to form a strapped contact, and applying a metallization layer over the strapped contact.