Buried Field Plate Isolation for Power Semiconductor Devices
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Solution Overview
Problem
Existing semiconductor manufacturing methods struggle to achieve effective isolation of power electronic devices from logic circuits without occupying excessive silicon area or incurring high manufacturing costs, particularly for high-side operation at high voltages, and lack practical alternatives to silicon-on-insulator structures.
Innovation Solution
A method involving the etching of laterally spaced longitudinal trenches in a semiconductor body, forming insulator on the trench sidewalls, creating continuous cavities at the trench bases that join to form a single laterally extending cavity, and filling these cavities with materials like high-K dielectrics or conductors to form buried field plates, which reduces sensitivity to alpha particles and allows for flexible material use.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon-on-insulator wafers are used for isolation, then effective isolation and shielding of power devices is achieved, but manufacturing cost increases significantly
Solution Approach 1:
The isolation structure is segmented into multiple components: trenches extending from the surface, cavities formed at the trench bases, and insulator material filling the cavities. This segmentation allows achieving SOI-like isolation effects through conventional bulk silicon processing, avoiding the high cost of actual SOI wafers while maintaining effective electrical isolation and shielding
Solution Approach 2:
An insulator material is introduced as an intermediary substance filling the cavities formed beneath the semiconductor region. This insulator layer acts as the mediating element that provides the electrical isolation and shielding functions typically associated with SOI structures, but can be implemented using standard processing materials and techniques
2Ease of manufacture
If discrete cavities are etched at the base of trenches, then manufacturing flexibility is reduced, but process simplicity is maintained
Solution Approach 1:
The cavities at the bases of adjacent trenches are merged to form a continuous cavity structure. This merging enables the use of a wide variety of filling materials including conductors, semiconductors, and insulators, providing manufacturing flexibility comparable to SOI technology while maintaining the simplicity of the trench-based formation process
Solution Approach 2:
The cavity structure is designed to accommodate different material phases and properties. By forming continuous cavities that can be filled with various materials (conductive, semiconductive, or insulating), the structure allows parameter changes in material selection without changing the fundamental cavity formation process, enabling adaptability across different device requirements
3Productivity
If power devices are integrated with logic circuits, then component density increases, but isolation requirements become more stringent
Solution Approach 1:
The isolation structure uses a nested configuration where trenches extend from the surface downward, cavities are formed at the trench bases, and insulator material is nested within the cavities. This nested structure provides multi-layer isolation that effectively shields power devices from logic circuits, enabling safe integration while maintaining stringent isolation requirements
Solution Approach 2:
The isolation approach extends into the vertical dimension by forming trenches and cavities beneath the semiconductor surface. This vertical dimensionality provides isolation paths that extend below the active device regions, effectively separating power and logic circuits in the depth direction while allowing their horizontal integration on the same substrate
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides effective isolation for power semiconductor devices, reduces sensitivity to alpha particles, and integrates power devices with logic circuits on the same substrate without the expense and complexity of silicon-on-insulator technology, while allowing for flexible material choices and reduced peak electrical fields.
Implementation Method 1
etching a plurality of laterally spaced longitudinal trenches from the first major surface towards the second major surface
Implementation Method 2
forming insulator on the sidewalls of the trenches to protect at least part of the sidewalls from etching
Implementation Method 3
filling the cavities with materials like high-K dielectrics or conductors to form buried field plates
Data Source
AI summary
A semiconductor device is formed with a lower field plate (32) and optional lateral field plates (34) around semiconductor (20) in which devices are formed, for example power FETs or other transistor or diode types. The semiconductor device is manufactured by forming trenches with insulated sidewalls, etching cavities (26) at the base of the trenches which join up and then filling the trenches with conductor (30).