Buried Gate Electrode Structure Using 2D Material to Reduce GIDL

The patent applies local quality by creating a multi-layer gate insulating structure with different dielectric materials positioned at specific locations. A first gate insulating layer with lower dielectric constant is placed adjacent to the drain area to suppress GIDL, while a second gate insulating layer with higher dielectric constant is placed in other regions to maintain strong gate control and device performance. This spatial differentiation of material properties resolves the contradiction between device miniaturization and performance maintenance.

The patent employs composite materials by combining gate insulating layers with different dielectric constants in a single gate structure. The first gate insulating layer (lower dielectric constant) and second gate insulating layer (higher dielectric constant) work together to simultaneously achieve reduced GIDL effect and maintained device performance, allowing the device to be scaled down without sacrificing reliability.

The patent addresses leakage current by implementing local quality through a differentiated gate insulating structure. The first gate insulating layer with lower dielectric constant is specifically positioned in the region adjacent to the drain where GIDL occurs, locally suppressing the harmful leakage effect. This allows the transistor to be scaled down while maintaining low leakage current through targeted material placement rather than uniform structure modification.

The patent converts the harmful GIDL effect into a manageable issue by using the same gate insulating structure to both enable device scaling and suppress leakage. The multi-layer gate insulating structure, designed to improve gate control for smaller devices, inadvertently creates a dielectric interface that reduces the electric field at the drain junction, thereby converting the scaling benefit into a dual benefit that also suppresses leakage current.