Buried Gate Electrode Filling With ALD-ALE Trench Profile Control

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Solution Overview

Problem

In semiconductor manufacturing, the process of forming recessed gate structures can result in bent sidewall lines due to attractive forces and plasma damage to the substrate, leading to increased costs and reduced reliability.

Innovation Solution

A method involving repeated cycles of atomic layer deposition (ALD) and atomic layer etching (ALE) is used to form a buried gate electrode layer, where the ALE process preferentially etches conductive layers near trenches and their upper ends using low-energy ions and halogen-containing gases, with inert gas purges to minimize substrate damage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If high-energy plasma ions are used to etch the conductive material, then the etching efficiency is improved, but plasma damage to the semiconductor substrate is caused

Engineering Contradiction:
Improveetching efficiencyVSAvoidplasma damage to substrate
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent changes the energy parameter of ions from high-energy (conventional plasma etching) to low-energy (≤10 eV), fundamentally altering the etching mechanism to achieve selective removal of conductive material without plasma damage to the substrate. This parameter change enables precise control over etching depth and selectivity.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent replaces the conventional plasma-based etching mechanism with an atomic layer etching (ALE) process that uses sequential chemical adsorption and low-energy ion activation. This substitution eliminates the harmful high-energy plasma effects while maintaining effective material removal through controlled chemical reactions and low-energy physical activation.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Manufacturing precision

If conventional etching processes are used to form recessed gate structures, then the conductive material is removed, but side wall lines of trenches are bent due to attractive force

Engineering Contradiction:
Improvetrench profile controlVSAvoidside wall line bending
Core Design Contradiction:
Manufacturing precisionVSShape

Solution Approach 1:

The patent applies local quality by making the etching process highly selective to specific locations. The ALE process with low-energy ions and halogen-containing gases enables preferential etching at the trench bottom and side walls while leaving the upper portions and surrounding areas unaffected. This localized etching action prevents side wall line bending and maintains precise trench geometry.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent employs periodic action through cyclic repetition of the ALE process steps (adsorption of etchant, activation by low-energy ions, removal of etched material, and purification). This periodic cycling allows controlled, incremental removal of conductive material layer by layer, maintaining precise shape control throughout the etching process and preventing deformation of trench side walls.

Inventive Principle:
Principle #19Periodic action

3Manufacturing precision

If the conductive layer is deposited to fill the trenches, then the buried gate electrode layer is formed, but the conductive layer accumulates on upper ends and side walls that need to be removed

Engineering Contradiction:
Improveconductive layer placementVSAvoidadditional etching steps required
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by incorporating the selective removal capability directly into the deposition process through the integrated ALE steps. The low-energy ion activation and halogen-containing gas adsorption are performed during or immediately after conductive layer deposition, preemptively removing excess material from upper ends and side walls before subsequent processing steps. This prevents the need for additional separate etching operations.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent merges the deposition and selective removal operations into a single integrated ALE process cycle. The conductive layer formation and the selective etching of excess material are combined into alternating steps within the same process sequence, using the same low-energy ion and chemical etchant system. This merging simplifies the overall manufacturing process while achieving precise conductive layer placement.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces substrate damage and process costs by precisely controlling the etching of conductive layers within trenches, enhancing the reliability and efficiency of semiconductor device manufacturing.

Implementation Method 1

an atomic layer deposition (ALD) process for forming a conductive layer on the gate insulating layer

Methodology Applied
Scientific EffectAtomic layer deposition: Chemical Vapour Deposition

Implementation Method 2

an atomic layer etching (ALE) process for preferentially etching portions of the conductive layer formed near the one or more trenches and portions of the conductive layer formed on upper ends of the one or more trenches

Methodology Applied
Scientific EffectAtomic layer etching:

Implementation Method 3

removing portions of the conductive layer from the semiconductor substrate by activating portions of the etchant adsorbed onto the conductive layer by supplying ions onto the conductive layer in a direction perpendicular to the semiconductor substrate

Methodology Applied
Scientific EffectIon bombardment: Ion Beam

Implementation Method 4

adsorbing an etchant onto the conductive layer

Methodology Applied
Scientific EffectAdsorption: Adsorption

Data Source

PatentUS20240072142A1Semiconductor device and method of manufacturing the same
Publication Date: 2024.02.29 SYSTEM ENGINEERING MEGA SOLUTION CO LTD
  • US20240072142A1 patent drawing
  • US20240072142A1 patent drawing
  • US20240072142A1 patent drawing

AI summary

Provided is a method of manufacturing a semiconductor device, the method including steps of providing a semiconductor substrate having one or more trenches, forming a gate insulating layer on the semiconductor substrate inside the trenches, and forming a buried gate electrode layer on the gate insulating layer to at least partially fill the trenches, wherein the step of forming the buried gate electrode layer includes a step of repeating a unit cycle a plurality of times, the unit cycle including an atomic layer deposition (ALD) process for forming a conductive layer on the gate insulating layer to serve as the buried gate electrode layer, and an atomic layer etching (ALE) process for preferentially etching portions of the conductive layer formed near the trenches and portions of the conductive layer formed on upper ends of the trenches over other portions of the conductive layer inside the trenches.