Buried Gate Anti-Fuse Transistor for High-Density Memory Integration
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Solution Overview
Problem
Semiconductor devices face defects during manufacturing that affect their performance, particularly in memory cells, leading to issues with operating speed, storage capacity, integration, and reliability.
Innovation Solution
An anti-fuse device is designed with a program transistor that executes programming via insulation breakdown of a gate insulating layer and a read transistor adjacent to it, with at least one gate electrode buried in the substrate, allowing for a reduced size and increased integration while maintaining high operation speed through a buried cell array transistor structure and a planar structure for the program and read transistors respectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a planar transistor structure is used for both program and read transistors, then manufacturing is easier, but device area increases
Solution Approach 1:
The patent applies dimensionality change by transitioning from a planar transistor structure to a buried cell array transistor structure. The gate electrode is positioned at a deeper level within the substrate, utilizing the vertical dimension to reduce the horizontal footprint of the device. This allows the program transistor and read transistor to be arranged more compactly, thereby reducing overall device area while maintaining manufacturability through established semiconductor fabrication processes.
2Quantity of substance
If device size is reduced to increase integration, then storage capacity increases, but operating speed may deteriorate
Solution Approach 1:
By positioning the gate electrode at a deeper level in the substrate, the patent reduces the horizontal spacing between transistors, enabling higher density integration. The vertical positioning of the gate allows for optimized electrical characteristics that maintain operating speed despite reduced device dimensions, as the gate control remains effective through the gate insulating layer at the deeper level.
Solution Approach 2:
The patent applies local quality by using different transistor structures for the program transistor and read transistor. The program transistor utilizes the buried cell array structure with the gate electrode at a deeper level, while the read transistor uses a planar structure. This differentiation allows each transistor to be optimized for its specific function, maintaining overall device performance while achieving compact integration.
3Quantity of substance
If more memory cells are integrated, then storage capacity increases, but defects during manufacturing increase
Solution Approach 1:
The buried cell array structure with vertically positioned gate electrodes enables compact cell arrangement, increasing the number of memory cells per unit area. This dimensional approach allows higher integration density while maintaining uniform manufacturing conditions, as the deeper gate positioning provides better control over the thin gate insulating layer, thereby managing defect rates during fabrication.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The anti-fuse device achieves a significantly reduced total size while maintaining high operation speed and allowing for a pitched layout, enhancing manufacturing efficiency and addressing defects in semiconductor devices.
Implementation Method 1
a program transistor to execute a program via insulation breakdown of a gate insulating layer
Data Source
AI summary
An anti-fuse device includes a program transistor and a read transistor. The program transistor executes a program via insulation breakdown of a gate insulating layer. The read transistor is adjacent to the program transistor and reads the state of the program transistor. At least one of a first gate electrode of the program transistor or a second gate electrode of the read transistor is buried in a substrate.