Buried Gate Structure Buffer Oxide Layer Stress Relief
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Solution Overview
Problem
As the integration of semiconductor devices increases, the buried gate structure faces challenges due to compressive stress from hard insulating materials like silicon nitride, which affects the silicon substrate and reduces carrier mobility.
Innovation Solution
A semiconductor device with a buried gate structure featuring a recessed upper end of the gate barrier pattern, a buffer oxide layer, and a gate capping insulating layer is developed, reducing compressive stress and improving carrier mobility by using a softer and more flexible silicon oxide layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon nitride is used as the gate capping insulating layer, then the gate structure provides good electrical isolation, but compressive stress is applied to the silicon substrate due to thermal expansion coefficient differences
Solution Approach 1:
The patent employs a composite insulating layer structure consisting of a first gate capping insulating layer (silicon nitride) and a second gate capping insulating layer (silicon oxide) with different thermal expansion coefficients. This composite structure balances the compressive stress while maintaining electrical isolation functionality.
Solution Approach 2:
The patent introduces a second gate capping insulating layer made of silicon oxide with a thermal expansion coefficient closer to that of silicon substrate. This changes the thermal expansion parameter of the overall gate capping structure, thereby reducing the compressive stress applied to the substrate during thermal processes.
2Ease of manufacture
If the gate barrier pattern upper end is flush with the gate electrode pattern, then manufacturing is simpler, but gate-induced drain leakage current increases
Solution Approach 1:
The patent applies a protective coating material specifically at the upper end portion of the gate electrode pattern where the gate barrier pattern meets the gate electrode pattern. This localized treatment prevents harmful interactions at the critical interface region without affecting the overall manufacturing process complexity.
3Quantity of substance
If ion implantation is used to form source and drain areas, then doping is effective, but physical damage occurs to the substrate
Solution Approach 1:
The patent replaces the mechanical ion implantation process with a chemical diffusion process. The buffer oxide layer serves as a dopant source, allowing dopants to diffuse into the substrate through thermal energy rather than mechanical impact, thereby achieving effective doping without physical damage.
Solution Approach 2:
The buffer oxide layer acts as an intermediary between the dopant source and the silicon substrate. It provides a controlled diffusion path for dopants to reach the substrate, enabling effective doping while preventing the direct mechanical damage associated with ion implantation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design decreases gate-induced drain leakage current and mitigates the reduction in carrier mobility caused by thermal expansion coefficient differences, while allowing for the formation of source and drain areas without physical damage.
Implementation Method 1
Since a thermal expansion coefficient of silicon nitride may be significantly different from that of a silicon substrate, silicon nitride may cause a compressive stress to be applied to the silicon substrate during subsequent thermal processes
Implementation Method 2
the dopant in the buffer oxide layer may be diffused into the active region to form a source area and drain areas
Data Source
AI summary
A semiconductor device includes a device isolation region defining an active region in a substrate, and gate structures buried in the active region of the substrate. At least one of the gate structures includes a gate trench, a gate insulating layer conformally formed on an inner wall of the gate trench, a gate barrier pattern conformally formed on the gate insulating layer disposed on a lower portion of the gate trench, a gate electrode pattern formed on the gate barrier pattern and filling the lower portion of the gate trench, an electrode protection layer conformally formed on the gate insulating layer disposed on an upper portion of the gate trench to be in contact with the gate barrier pattern and the gate electrode pattern, a buffer oxide layer conformally formed on the electrode protection layer, and a gate capping insulating layer formed on the buffer oxide layer to fill the upper portion of the gate trench.