Buried Gate Semiconductor Device With Deep Isolation Trenches
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in reducing the total area occupied due to the large size of transistors with horizontal channel regions, which complicates the manufacturing process and leads to increased resistance and leakage current when using buried gates and BPSG interlayer insulating layers.
Innovation Solution
The semiconductor device employs a semiconductor substrate with deeper trenches for device isolation in the peripheral circuit region compared to the cell region, allowing for a buried gate in the cell region and a polysilicon gate in the peripheral circuit region, both at the same surface level, along with a bit line that contacts the substrate, to reduce area and improve manufacturing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a buried gate is formed entirely within a recess to reduce transistor area, then the area occupied by the transistor is reduced, but the manufacturing process becomes more complex and device degradation occurs due to simultaneous patterning of bit lines and gates
Solution Approach 1:
The patent divides the semiconductor device into two distinct regions: a cell region with buried gates for high-density storage, and a peripheral circuit region with conventional planar gates for control circuits. This segmentation allows each region to be optimized independently, with the cell region achieving area reduction through buried gates while the peripheral region maintains simpler manufacturing processes
Solution Approach 2:
Different gate structures are applied to different functional regions of the semiconductor device. The cell region uses buried gates entirely within the substrate to minimize area, while the peripheral circuit region uses conventional planar gates that extend to the surface for easier manufacturing and control, thus applying local quality differentiation to resolve the contradiction between area reduction and manufacturing complexity
2Manufacturing precision
If BPSG is used as the interlayer insulating layer to precisely bury bit lines, then bit line positioning is improved, but boron penetrates into the semiconductor substrate causing device degradation
Solution Approach 1:
The patent extracts the problematic BPSG interlayer insulating layer from the cell region where it causes boron penetration issues. Instead, the cell region uses a different insulating structure that allows precise bit line positioning without the harmful boron diffusion effect, while the peripheral region may still use BPSG where it is less problematic
Solution Approach 2:
The patent addresses the boron penetration issue by modifying the insulating layer structure to prevent harmful boron diffusion into the active region, thereby converting a potentially harmful material (BPSG with boron) into a controlled situation where the boron is contained and cannot degrade device performance
3Reliability
If spacers are thickly formed on gates to prevent boron penetration, then boron penetration is blocked, but contact area between active region and storage node contact is reduced increasing resistance
Solution Approach 1:
The patent segments the device structure into regions with different spacer configurations. In the cell region with buried gates, spacers are formed only on specific sides to protect against boron penetration while maintaining adequate contact area, whereas in the peripheral circuit region, thicker spacers may be used where contact area is less critical
4Manufacturing precision
If annealing process is performed after BPSG formation, then interlayer insulating layer properties are improved, but operation current is reduced and leakage current is increased
Solution Approach 1:
The patent extracts or eliminates the annealing process from the manufacturing sequence in regions where it causes excessive leakage current. Instead, alternative methods are used to achieve the necessary insulating layer properties without subjecting the device to high-temperature annealing that increases leakage and reduces operation current
Data Source
AI summary
A semiconductor device includes a semiconductor substrate including a cell area and a peripheral circuit area, a first trench for device isolation formed in the cell area of the semiconductor substrate and a second trench for device isolation formed within the semiconductor substrate of the peripheral circuit area to be deeper than the first trench, a device isolation layer buried within the first and second trenches for device isolation and having the same surface level as the semiconductor substrate in the cell area, a buried gate buried in the semiconductor substrate of the cell area, and a peripheral circuit gate which is in contact with the semiconductor substrate of the peripheral circuit area, is buried within the device isolation layer of the peripheral circuit area, and has the same surface level as the buried gate. It can prevent the same effect from affecting the cell area and the peripheral circuit area so that the number of masks is reduced and the process is simplified so that cost can be reduced and characteristics of the semiconductor device can be improved.