Buried Gate Structure Formation via Sequential Deposition and Etching
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Solution Overview
Problem
The manufacturing of semiconductor devices faces challenges in filling high aspect ratio trenches, leading to defects such as overhangs and voids due to the complexity of integration and miniaturization, which affects device performance.
Innovation Solution
A method involving sequential deposition and etching processes is employed to form a gate electrode layer, where a first deposition process is followed by a first etching process to widen gaps and reduce thickness, and subsequent deposition and etching processes are repeated to prevent defects and reduce stress, ultimately forming a buried gate structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single deposition process is used to form the gate electrode layer, then the manufacturing process is simpler and faster, but defects such as overhangs and voids are formed in the conductive structure
Solution Approach 1:
The gate electrode layer formation is divided into multiple deposition processes (first deposition, second deposition, third deposition) with etching processes in between. This segmentation allows each deposition step to deposit material more uniformly without forming overhangs or voids, while the etching steps remove excess material to create proper gaps. The multi-step approach maintains manufacturing efficiency while significantly improving filling quality and preventing defects.
2Reliability
If the gate electrode material is deposited thicker to ensure complete coverage, then coverage is improved, but stress on the semiconductor substrate increases
Solution Approach 1:
The gate electrode layer is formed through multiple thin deposition layers (first, second, and third gate electrode materials) rather than a single thick layer. Each thin layer deposits material with adequate coverage while minimizing stress accumulation. The etching processes between deposition steps further control the final thickness and create gaps that reduce overall stress on the substrate, maintaining both coverage quality and substrate stress levels.
3Manufacturing precision
If multiple deposition and etching processes are used to form the gate electrode layer, then defects are prevented and stress is reduced, but the manufacturing process becomes more complex
Solution Approach 1:
The gate electrode layer formation is segmented into multiple deposition and etching processes, where each step serves a specific function: first deposition creates initial coverage, first etching widens gaps and removes excess material, second deposition adds more material, and third deposition completes the layer. This segmentation improves manufacturing precision by preventing overhangs and voids while controlling stress, and the systematic nature of the segmented process makes it manageable despite the increased number of steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents the formation of defects like overhangs and voids, reduces stress on the semiconductor substrate, and enhances overall device performance by ensuring a more reliable and efficient gate electrode layer formation.
Implementation Method 1
performing a first deposition process... depositing a first gate electrode material over the gate dielectric layer and the top surface of the semiconductor substrate
Implementation Method 2
performing a first etching process... etching the first gate electrode material... the first etching process and the second etching process are dry etching processes
Data Source
AI summary
A method for forming a semiconductor device includes forming a trench extending from a top surface of a semiconductor substrate into the semiconductor substrate, and forming a gate dielectric layer lining the trench. The method also includes forming a gate electrode layer in the trench and over the top surface of the semiconductor substrate. The formation of the gate electrode layer includes performing a first deposition process, performing a first etching process after the first deposition process, and performing a second deposition process after the first etching process.