Buried Gate Depth Layout for Array and Periphery Conductivity
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Solution Overview
Problem
Existing semiconductor manufacturing processes do not differentiate between dense and loose areas, leading to inefficient component design and performance variations.
Innovation Solution
A semiconductor structure with distinct buried gate structures in array and periphery regions, where the first buried gate structure in the array region has a shallower depth and narrower width than the second buried gate structure in the periphery region, allowing for wider channels and improved current conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the same manufacturing process is used for both dense and loose areas, then manufacturing simplicity is maintained, but component performance and efficiency are compromised due to inadequate differentiation
Solution Approach 1:
The substrate is divided into distinct array region and periphery region, with separate manufacturing processes applied to each region. The array region receives a first manufacturing process while the periphery region receives a second manufacturing process, allowing optimization for different functional requirements while maintaining overall manufacturing simplicity through systematic differentiation.
Solution Approach 2:
Different manufacturing parameters and processes are applied to different regions of the substrate. The array region and periphery region receive tailored processes optimized for their specific functional requirements, enabling each region to achieve optimal performance characteristics appropriate to its local needs.
2Reliability
If deeper buried gate structures are used in the array region, then better control over channel conductivity is achieved, but current conductivity is reduced in the periphery region where wider channels are needed
Solution Approach 1:
The buried gate structure depth is differentiated by region: the array region receives a first buried gate structure at a first depth optimized for control, while the periphery region receives a second buried gate structure at a second depth optimized for current conductivity. This local differentiation allows each region to achieve optimal performance for its specific function.
Solution Approach 2:
The buried gate structure is segmented into region-specific implementations with different depths and characteristics. The first buried gate structure in the array region and the second buried gate structure in the periphery region are manufactured with distinct parameters to satisfy different electrical requirements.
3Productivity
If narrower channels are used in the array region, then higher density is achieved, but current conductivity is limited; if wider channels are used, then better current conductivity is achieved but density is reduced
Solution Approach 1:
Channel width is optimized locally for each region's functional requirements. The array region implements narrower channels to maximize component density, while the periphery region implements wider channels to maximize current conductivity. Each region achieves its optimal balance between density and conductivity appropriate to its function.
Data Source
AI summary
The present application discloses a semiconductor device including a substrate, a first buried gate structure, and a second buried gate structure. The substrate has an array region and a periphery region. The first buried gate structure is extended from a first surface of the substrate along a first direction into the substrate and disposed in the array region. The second buried gate structure is extended from the first surface of the substrate along the first direction into the substrate and disposed in the periphery region. A depth of the first buried gate structure is less than a depth of the second buried gate structure along the first direction.