Buried Gate DRAM Fabrication via Non-Plasma Etching

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Solution Overview

Problem

Current DRAM units with buried gate structures face limitations in fabrication capability, affecting performance and reliability due to challenges in etching processes that can damage adjacent elements.

Innovation Solution

A method involving a substrate with defined memory regions, forming trenches, barrier, and conductive layers, followed by specific etching processes, including a non-plasma etching process to remove parts of the barrier layer without damaging adjacent elements, resulting in improved gate electrodes for DRAM devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional plasma etching process is used to remove barrier layer, then etching efficiency is improved, but adjacent elements are damaged

Engineering Contradiction:
Improveetching efficiencyVSAvoiddamage to adjacent elements
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent replaces the plasma etching process (chemical/physical system) with a non-plasma etching process. This substitution eliminates the harmful plasma effects that damage adjacent elements while maintaining the ability to remove the barrier layer, thus resolving the contradiction between etching efficiency and element damage.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent changes the fundamental parameter of the etching process by transitioning from plasma-based to non-plasma-based etching. This parameter change alters the mechanism of material removal, achieving barrier layer removal without the collateral damage caused by plasma to surrounding sensitive structures.

Inventive Principle:
Principle #35Parameter changes

2Manufacturing precision

If multiple etching processes are used to remove conductive layer and barrier layer, then fabrication precision is improved, but process complexity increases

Engineering Contradiction:
Improveetching precisionVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent segments the etching process into two distinct stages: first removing the conductive layer, then removing the barrier layer. Each stage uses an optimized etching approach, with the second stage specifically employing non-plasma etching. This segmentation allows precise control over what is removed at each step, achieving high fabrication precision while managing process complexity through clear separation of functions.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enhances the fabrication of DRAM devices by improving etching precision and reducing damage to adjacent elements, leading to increased performance and reliability of buried word lines and capacitor structures.

Implementation Method 1

performing a second etching process to remove part of the barrier layer. Preferably, the second etching process comprises a non-plasma etching process.

Methodology Applied
Scientific EffectNon-plasma etching:

Data Source

PatentUS9887088B1Method for fabricating semiconductor device
Publication Date: 2018.02.06 UNITED MICROELECTRONICS CORP
  • US9887088B1 patent drawing
  • US9887088B1 patent drawing
  • US9887088B1 patent drawing

AI summary

A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region defined thereon; forming a trench in the substrate; forming a barrier layer in the trench; forming a conductive layer on the barrier layer; performing a first etching process to remove part of the conductive layer; and performing a second etching process to remove part of the barrier layer. Preferably, the second etching process comprises a non-plasma etching process.