Buried Gate DRAM With High-k Capping Layer

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Solution Overview

Problem

In semiconductor devices, particularly dynamic random access memory (DRAM) devices, the buried gate structure faces challenges with leakage current and resistance issues due to the protruding gate electrode and high impurity doping requirements, which affect the current drivability and stability of transistors.

Innovation Solution

A semiconductor device with a buried gate electrode and a capping layer pattern using a high-k material layer with a dielectric constant greater than 10, combined with a low-k material layer, to reduce resistance and leakage current by optimizing the impurity doping and electric field distribution.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If high concentration impurity doping is applied to source/drain regions to reduce resistance, then ohmic contact is improved, but junction leakage current increases due to increased electric field

Engineering Contradiction:

Improveohmic contact qualityVSAvoidjunction leakage current

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent applies different impurity concentrations to different regions: high concentration in lower source/drain regions for ohmic contact, and low concentration in upper source/drain regions adjacent to the capping layer to minimize leakage current. This spatial differentiation of doping concentration resolves the contradiction between achieving low resistance and preventing junction leakage.

Inventive Principle:

Principle #3Local quality

2Productivity

If protruding gate electrode is used to reduce transistor size, then integration density is improved, but contact plug formation and planarization processes become more difficult

Engineering Contradiction:

Improveintegration densityVSAvoidcontact plug formation and planarization

Core Design Contradiction:

ProductivityVSEase of manufacture

Solution Approach 1:

Instead of having the gate electrode protrude upward from the substrate surface, the patent inverts the structure by burying the gate electrode below the substrate surface and using a capping layer to bring the gate control function to the appropriate level. This inversion resolves the manufacturing difficulties associated with protruding gates while maintaining the benefits of reduced transistor size.

Inventive Principle:

Principle #13The other way round (Inversion)

3Productivity

If protruding gate electrode is used to reduce transistor size, then integration density is improved, but edge portion of depressed channel region causes leakage current due to field crowding effect

Engineering Contradiction:

Improveintegration densityVSAvoidleakage current from field crowding

Core Design Contradiction:

ProductivityVSObject-generated harmful factors

Solution Approach 1:

The patent changes the geometric parameters of the gate structure by burying the gate electrode and using a capping layer with specific dielectric properties. This parameter change modifies the electric field distribution, reducing the field crowding effect at the channel edges while maintaining the compact transistor structure needed for high integration density.

Inventive Principle:

Principle #35Parameter changes

4Ease of manufacture

If buried gate electrode is used to resolve protruding gate issues, then manufacturing complexity is reduced, but source/drain region resistance increases due to inappropriate doping concentration

Engineering Contradiction:

Improvemanufacturing process simplicityVSAvoidsource/drain region resistance

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The patent applies different impurity concentrations to different vertical regions of the source/drain structures. High concentration doping is applied to lower regions for ohmic contact, while low concentration doping is applied to upper regions adjacent to the capping layer. This local differentiation resolves the resistance issue while maintaining the manufacturing simplicity of the buried gate structure.

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution improves current attributes and reduces leakage current in DRAM devices by enhancing the fringing field effect and reducing the electric field at the surface, thereby increasing current drivability and stability of the transistors.

Implementation Method 1

improving current attributes and reducing leakage current by enhancing the fringing field effect

Methodology Applied

Scientific EffectFringing field effect: Electric Field

Implementation Method 2

capping layer pattern using a high-k material layer with a dielectric constant greater than 10... reducing leakage current by optimizing the impurity doping and electric field distribution

Methodology Applied

Scientific EffectDielectric effect: Dielectric

Data Source

PatentUS8610191B2Semiconductor devices and dynamic random access memory devices including buried gate pattern with high-k capping layer

Publication Date: 2013.12.17 SAMSUNG ELECTRONICS CO LTD

AI summary

Semiconductor devices and dynamic random access memory devices including a buried gate electrode are provided, the semiconductor devices include a substrate with a gate trench, a buried gate electrode partially filling the inside of the gate trench, a capping layer pattern in the gate trench and over the buried gate electrode, source/drain regions below an upper surface of the substrate and adjacent to both sides of the buried gate electrode, and a gate insulation layer interposed between the trench and the buried gate electrode. The capping layer pattern includes a high-k material layer that directly contacts an upper surface of the buried gate electrode.