Buried Gate DRAM Fabrication for Leakage Reduction
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Solution Overview
Problem
Current DRAM units with buried gate structures face limitations in fabrication capability, affecting performance and reliability due to challenges in achieving higher integration and density.
Innovation Solution
A method involving a substrate with defined memory and periphery regions, forming buried gates, epitaxial layers, and multiple silicon layers through specific etching and deposition processes to enhance device fabrication, including selective epitaxial growth and multi-stage etching to improve smoothness and integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional DRAM units with planar gate structures are used, then fabrication process is simpler, but carrier channel length is shorter leading to increased capacitor leakage
Solution Approach 1:
The fabrication process is divided into multiple stages: first forming buried gates in the memory region, then selectively forming silicon layers in periphery regions, and finally forming epitaxial layers between buried gates. This segmentation allows complex buried gate structures to be built through manageable sequential steps, resolving the contradiction between reliability improvement and fabrication complexity.
Solution Approach 2:
Different regions of the substrate receive different treatments: memory regions get buried gates for leakage reduction, periphery regions get silicon layers for device formation, and regions between buried gates get epitaxial layers. This local differentiation enables the buried gate structure to improve capacitor leakage while maintaining overall device functionality.
2Productivity
If higher integration and density are pursued, then device capacity increases, but fabrication capability limitations cause performance and reliability degradation
Solution Approach 1:
The patent transitions from planar gate structures to three-dimensional buried gate structures extending into the substrate. This dimensional change enables higher integration density while maintaining reliable electrical characteristics, as the buried gates provide longer carrier channel length vertically rather than horizontally, overcoming fabrication capability limitations.
Solution Approach 2:
Buried gates are formed in advance before subsequent silicon layer and epitaxial layer formation. This preliminary action establishes the foundation for high-density integration while ensuring reliable device performance from the outset, rather than attempting to achieve density first and then address performance issues.
3Manufacturing precision
If selective epitaxial growth is used to form layers between buried gates, then smoothness and integration improve, but process complexity increases
Solution Approach 1:
Epitaxial layers are formed as intermediary structures between the buried gates and the silicon layers on periphery regions. These intermediate layers provide a smooth transition zone that improves manufacturing precision and layer uniformity, while the multi-stage process, though complex, systematically builds the structure in controllable increments.
Solution Approach 2:
The fabrication process employs continuous deposition and etching operations to build up silicon layers and epitaxial layers uniformly across different regions. This continuous action ensures smooth layer formation and high integration quality, with each stage building upon the previous one to maintain process control despite increasing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method improves the performance and reliability of DRAM devices by enabling better integration and reducing capacitor leakage, enhancing the overall fabrication process efficiency and device quality.
Implementation Method 1
forming an epitaxial layer on the substrate between the first buried gate and the second buried gate
Data Source
AI summary
A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region and a periphery region; forming a first buried gate and a second buried gate in the substrate on the memory region; forming a first silicon layer on the substrate on the periphery region; forming a stacked layer on the first silicon layer; forming an epitaxial layer on the substrate between the first buried gate and the second buried gate; and forming a second silicon layer on the epitaxial layer on the memory region and the stacked layer on the periphery region.