Buried Gate Fabrication via Dual Recess Etching

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Solution Overview

Problem

Conventional methods for fabricating buried gates in semiconductor devices result in damage to the gate insulation layer at the top corners of trenches during the plasma dry etch process, leading to a deterioration of the refresh characteristic.

Innovation Solution

A method involving a first recess process using a wet etch process followed by a second recess process with a protection pattern to protect the gate insulation layer during the dry etch, minimizing plasma damage and maintaining the integrity of the gate insulation layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If a plasma dry etch process is used to recess the gate conductive layer for forming buried gates, then the gate conductive layer can be effectively recessed to the required depth, but the gate insulation layer at the top corners of trenches suffers from over-etching and plasma damage, leading to thinning and deterioration of refresh characteristic

Engineering Contradiction:
Improverecess depth controlVSAvoidplasma damage to gate insulation layer
Core Design Contradiction:
Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

The single recess process is divided into two separate processes: a first recess process that recesses the gate conductive layer to an intermediate depth, and a second recess process that completes the recess to the final depth. This segmentation allows the gate insulation layer to be protected during the first process while enabling complete recess in the second process, thereby resolving the contradiction between achieving sufficient recess depth and preventing plasma damage to the gate insulation layer.

Inventive Principle:
Principle #1Segmentation

2Reliability

If the gate insulation layer is fully protected during etching, then the refresh characteristic is maintained, but the etching process cannot achieve the required recess depth for proper buried gate formation

Engineering Contradiction:
Improverefresh characteristicVSAvoidrecess depth
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The first recess process is performed as a preliminary action before the second recess process. This preliminary recess removes sufficient gate conductive layer material to enable proper buried gate formation, while the gate insulation layer remains protected at this stage. The protection is maintained through the second recess process, ensuring both adequate recess depth and preservation of gate insulation layer integrity for maintaining refresh characteristic.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method effectively reduces damage to the gate insulation layer at the top corners of trenches, preventing deterioration of the refresh characteristic and ensuring uniformity and reliability of the buried gates.

Implementation Method 1

performing a first recess process by etching the gate conductive layer

Methodology Applied
Scientific EffectWet etching:

Implementation Method 2

performing a second recess process by etching the gate conductive layer

Methodology Applied
Scientific EffectPlasma dry etching: Plasma

Data Source

PatentUS8153489B2Method for fabricating semiconductor device with buried gates
Publication Date: 2012.04.10 SK HYNIX INC
  • US8153489B2 patent drawing
  • US8153489B2 patent drawing
  • US8153489B2 patent drawing

AI summary

A method for fabricating a semiconductor device, including forming a trench by etching a semiconductor substrate, forming a gate insulation layer over a surface of the trench, forming a gate conductive layer over the gate insulation layer, performing a first recess process by etching the gate conductive layer, forming a protection pattern over the gate insulation layer, and performing a second recess process by etching the gate conductive layer.