Buried Gate Electrode Sidewall Patterning for GIDL Reduction
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Solution Overview
Problem
The buried word line structure in semiconductor devices experiences increased Gate Induced Drain Leakage (GIDL) due to overlap between the gate electrode material and the junction, leading to deteriorated refresh characteristics and higher resistance, which complicates the reduction of parasitic capacitance and maintenance of operational reliability.
Innovation Solution
A method for manufacturing semiconductor devices that involves forming a gate electrode pattern at the sidewalls of the active region, including a source region, by etching the gate electrode material anisotropically and forming a capping layer to prevent overlap with the junction, thereby reducing GIDL and adjusting the junction depth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate electrode material is extended to cover the junction region to improve gate control, then the gate control is improved, but the Gate Induced Drain Leakage (GIDL) increases
Solution Approach 1:
The patent applies local quality by forming the gate electrode material only in specific locations (recesses) rather than uniformly across the entire surface. The gate electrode is selectively positioned to provide control where needed while avoiding the junction region to prevent GIDL, creating different structural qualities in different areas of the device.
Solution Approach 2:
The gate electrode structure is segmented into discrete portions located in recesses rather than forming a continuous layer. This segmentation allows the gate to control specific regions while maintaining separation from the junction, thereby reducing GIDL while preserving necessary gate control functionality.
2Object-generated harmful factors
If the gate electrode material is etched back to reduce overlap with the junction to decrease GIDL, then the GIDL is reduced, but the gate control capability deteriorates
Solution Approach 1:
The patent transitions from a two-dimensional planar gate structure to a three-dimensional structure by forming recesses in the substrate. The gate electrode material is deposited conformally in these recesses, creating vertical sidewalls that provide enhanced gate control through the vertical dimension while the horizontal extent is limited to avoid junction overlap and reduce GIDL.
Solution Approach 2:
The gate electrode is positioned locally within recesses rather than as a continuous layer, providing concentrated gate control exactly where the recesses are formed while maintaining separation from the junction region. This localized positioning reduces GIDL while preserving control capability at critical locations.
3Productivity
If the channel length is decreased to increase integration density, then the integration density is improved, but the short channel effect and Drain Induced Barrier Lower (DIBL) increase
Solution Approach 1:
The patent addresses short channel effects by transitioning to a three-dimensional gate structure with vertical sidewalls formed in recesses. This vertical dimension provides enhanced electrostatic control over the channel, effectively increasing the gate's control authority without requiring a longer horizontal channel length, thereby maintaining high integration density while reducing short channel effects and DIBL.
Solution Approach 2:
The patent changes the geometric parameters of the gate structure by forming recesses with specific depth and width ratios. This parameter change creates a structure where the gate extends vertically along the sidewalls, increasing the effective gate control area and improving electrostatic control to counteract short channel effects even when the channel length is short for high integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively minimizes GIDL, prevents the gate electrode material from overlapping with the junction, and improves channel resistance, enhancing the operational reliability and refresh characteristics of semiconductor devices.
Implementation Method 1
forming a gate electrode pattern by etching the gate electrode material, wherein the gate electrode pattern is formed at sidewalls of the active region
Implementation Method 2
forming a capping layer in the exposed active region
Data Source
AI summary
A semiconductor device and a method for manufacturing the same are disclosed, which can form a gate electrode material only in a recess of a buried gate cell structure, improve a Gate Induced Drain Leakage (GIDL) of a gate electrode material and a junction (i.e., drain region), prevent the gate electrode material from overlapping with the junction (i.e., drain region), and adjust the depth of junction, thereby improving channel resistance. The method for manufacturing a semiconductor device includes forming a device isolation region defining an active region over a semiconductor substrate, burying a gate electrode material in the semiconductor substrate, forming a gate electrode pattern by etching the gate electrode material, wherein the gate electrode pattern is formed at sidewalls of the active region including a source region, and forming a capping layer in the exposed active region.