Buried Gate Electrode Structure for Semiconductor Devices
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Solution Overview
Problem
Current semiconductor devices with buried word lines face limitations in current driving capability and are vulnerable to body effects due to their structural constraints, which hinder high integration density and effective channel length.
Innovation Solution
A semiconductor device with a buried gate electrode structure is developed, featuring a gate trench with multiple layers and an insulating pattern, where the gate electrode fills a portion of the trench and covers the sidewalls of the active region, extending under the gate electrode, and an insulating pattern is formed to fill the remaining trench, enhancing effective channel length and width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If a buried word line structure is used to increase effective channel length, then the effective channel length is improved, but the effective channel width remains the same as planar MOSFET, resulting in inferior current driving capability
Solution Approach 1:
The gate electrode extends not only across the channel region but also underneath the active region in the vertical dimension, creating a three-dimensional buried gate structure. This dimensional change allows the gate to control a wider effective channel width while maintaining increased effective channel length, thereby improving current driving capability without sacrificing the benefits of extended channel length
2Length of moving object
If the insulated gate electrode protrudes over the semiconductor substrate to achieve longer effective channel length, then the effective channel length is improved, but subsequent processes such as contact plug formation and planarization are precluded
Solution Approach 1:
The gate electrode is nested within a trench structure that extends into the semiconductor substrate. The trench provides containment for the gate electrode, allowing it to extend underneath the active region while the trench walls and isolation layer provide structural support. This nesting approach enables the gate to achieve extended effective channel length while maintaining a planar upper surface that is compatible with subsequent contact plug formation and planarization processes
3Reliability
If a recessed channel region is used to downscale the transistor and overcome short channel effect, then the short channel effect is diminished, but upper corners of the recessed channel region cause leakage current due to field crowding effect
Solution Approach 1:
The gate electrode is extracted from the traditional position above the channel and placed underneath the active region in a buried configuration. This extraction removes the gate from positions where it could create field crowding at the upper corners of the channel region, thereby eliminating the source of leakage current while maintaining the recessed channel structure's ability to mitigate short channel effects
4Reliability
If the gate electrode covers the sidewalls of the active region and extends underneath to increase effective channel width, then the current driving capability is improved, but the device complexity increases
Solution Approach 1:
The gate electrode structure is segmented into distinct functional regions: a first portion that covers the sidewalls of the active region to maximize effective channel width, and a second portion that extends underneath the active region to increase effective channel length. The trench structure is also segmented with an isolation layer at the bottom providing a boundary. This segmentation allows each portion to be optimized for its specific function while maintaining manufacturability through defined fabrication steps
Data Source
AI summary
A semiconductor device includes an isolation layer disposed in a semiconductor device to define an active region. A gate trench is disposed across the active region and extends to the isolation layer. An insulated gate electrode fills a portion of the gate trench and covers at least one sidewall of the active region. A portion of the gate electrode, that covers at least one sidewall of the active region, extends under a portion of the gate electrode that crosses the active region. An insulating pattern is disposed on the gate electrode.