Buried Gate Dielectric Layout for Stable High-Voltage FDMOS
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Solution Overview
Problem
Conventional field-drift metal-oxide semiconductor (FDMOS) transistors experience instability at operation voltages exceeding 10V due to parasitic field devices, which affects the stability and performance of high-voltage circuits.
Innovation Solution
A semiconductor high-voltage device design featuring a semiconductor substrate with a high-voltage well, drift region, recessed channel region, heavily doped drain region, isolation structure, and buried gate dielectric layer, where the top surface of the buried gate dielectric layer is lower than the heavily doped drain region, and the isolation structure has varying thicknesses to enhance threshold voltage and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional FDMOS structure is used, then high voltage capability is achieved, but parasitic field devices turn on at operation voltages exceeding 10V causing instability
Solution Approach 1:
The device structure is segmented into distinct regions including a recessed channel region, isolation structure, and heavily doped drain region. The channel is divided into a first channel region over the isolation structure and a second channel region adjacent to the drift region, preventing parasitic field device activation while maintaining high voltage capability
Solution Approach 2:
Different regions of the device are given different doping concentrations and structural properties. The isolation structure has varying thickness (first thickness adjacent to channel, second thickness adjacent to drift region), and the heavily doped drain region has high doping concentration to locally control electric field distribution and suppress parasitic effects
2Reliability
If isolation structure with uniform thickness is used, then manufacturing is simplified, but threshold voltage control and stability are insufficient
Solution Approach 1:
The isolation structure is designed with non-uniform thickness, having a first thickness adjacent to the recessed channel region and a second thickness adjacent to the heavily doped drain region. This local variation in thickness enables precise control of the threshold voltage of parasitic field devices while maintaining manufacturing feasibility through standard semiconductor processing techniques
3Reliability
If buried gate dielectric layer top surface is aligned with drain region top surface, then device structure is simplified, but electrical properties and stability at high voltage are compromised
Solution Approach 1:
The top surface of the buried gate dielectric layer is positioned at a lower level than the top surface of the heavily doped drain region, creating an asymmetric structure. This asymmetric positioning optimizes the electric field distribution under high voltage conditions, improving electrical stability without requiring complex additional structures
Data Source
AI summary
A semiconductor high-voltage device includes a semiconductor substrate; a high-voltage well in the semiconductor substrate; a drift region in the high-voltage well; a recessed channel region adjacent to the drift region; a heavily doped drain region in the drift region and spaced apart from the recessed channel; an isolation structure between the recessed channel region and the heavily doped drain region in the drift region; a buried gate dielectric layer on the recessed channel region, wherein the top surface of the buried gate dielectric layer is lower than the top surface of the heavily doped drain region; and a gate on the buried gate dielectric layer.