Buried Gate Field Effect Transistor for Charge Retention
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Solution Overview
Problem
Existing field effect transistors, such as 1T-DRAM cells and PROM cells, face challenges in controlling threshold voltage due to insufficient contact area between floating gates and channel layers, leading to charge leakage and parasitic current paths, which limits their performance and integration capabilities.
Innovation Solution
A field effect transistor with a buried gate pattern electrically isolated by a tunneling insulating film, surrounded by a semiconductor material, which extends into the source and drain regions, allowing for enhanced charge storage and control of threshold voltage, and is fabricated using a method involving trench etching and semiconductor material filling to ensure efficient charge carrier storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If source/drain regions directly contact the floating body to enable carrier accumulation, then writing capability is improved, but charge leakage occurs during reading due to formed charge leakage paths
Solution Approach 1:
The invention segments the contact between source/drain regions and floating body by introducing an insulating layer at the interface. This allows the structure to simultaneously achieve electrical contact for writing (through the insulating layer's tunneling or thin-film conduction) and electrical isolation for reading (by blocking direct carrier leakage paths), thus resolving the contradiction between writing capability and charge retention.
2Stability of the object's composition
If the bottom surface of the channel layer contacts the substrate to provide structural support, then mechanical stability is improved, but the contact area between floating gate and channel layer becomes insufficient, limiting threshold voltage control
Solution Approach 1:
The invention transitions from a planar contact geometry to a three-dimensional configuration by extending the floating gate vertically and positioning it adjacent to the channel layer's side surface. This dimensional change dramatically increases the contact area between floating gate and channel layer, enabling precise threshold voltage control while the channel layer's bottom surface remains in contact with the substrate for mechanical stability.
3Productivity
If the distance between source/drain regions and first diffusion region is reduced to increase integration density, then device integration is improved, but parasitic current paths are formed through the source region, first diffusion region, and drain region
Solution Approach 1:
The invention introduces an insulating layer as an intermediary between the source/drain regions and the first diffusion region. This insulating layer acts as a barrier that blocks parasitic current paths while allowing the regions to be positioned closer together for increased integration density. The insulating layer mediates between the conflicting requirements of high integration and low parasitic current.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively stores charge carriers, reducing leakage and parasitic currents, enabling improved operation and integration in memory devices by fully depleting the channel region and allowing for non-destructive read operations while suppressing short channel effects.
Implementation Method 1
A field effect transistor with a buried gate pattern electrically isolated by a tunneling insulating film... storing charge for affecting a threshold voltage of the field effect transistor
Data Source
AI summary
A field effect transistor includes a buried gate pattern that is electrically isolated by being surrounded by a tunneling insulating film. The field effect transistor also includes a channel region that is floated by source and drain regions, a gate insulating film, and the tunneling insulating film. The buried gate pattern and the tunneling insulating film extend into the source and drain regions. Thus, the field effect transistor efficiently stores charge carriers in the buried gate pattern and the floating channel region.