Buried-Gate FET Structure With Tapered Channel for RF Linearity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional field-effect transistors (FETs) face issues such as current collapse, high vertical electric field-induced stress, degraded electrostatic isolation, limited linearity, and increased junction temperature due to top gate contact configurations, which affect their RF power performance, frequency operation, and reliability.
Innovation Solution
The implementation of buried gate structures with a tapered channel layer, where the gates contact the epitaxial channel layer only from the sides, allowing for lateral gating and modulation of channel width to control drain current, thereby engineering improved transfer characteristics and linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a top gate contact configuration is used, then the device structure is simple and easy to manufacture, but current collapse occurs due to electron trapping at the drain end of the gate, degrading RF power performance
Solution Approach 1:
The gate contact is extracted from the top surface and repositioned to the bottom of the device. The gate electrode is embedded in the substrate with its active region at the bottom, eliminating the top gate contact configuration that causes electron trapping and current collapse while maintaining manufacturing feasibility through modified fabrication processes
Solution Approach 2:
The gate structure is inverted from the conventional top-contact configuration to a bottom-contact configuration. The gate electrode is positioned at the bottom of the substrate rather than on the top surface, fundamentally changing the electric field distribution to eliminate the harmful vertical field at the drain end while preserving the gating function
2Device complexity
If a top gate contact configuration is used, then the device structure is simple, but high vertical electric field induces tensile stress causing cracks in epitaxial layers, limiting reliability
Solution Approach 1:
The problematic vertical gate field is extracted/eliminated by removing the top gate contact. The gate is repositioned to the bottom, replacing the vertical field mechanism with a lateral field mechanism that does not induce tensile stress in the epitaxial layers, thereby preventing cracks and improving device reliability
Solution Approach 2:
The invention converts the harmful vertical electric field effect into a beneficial lateral field configuration. By inverting the gate structure, the strong vertical field that caused piezoelectric stress and cracks is replaced with a lateral field that achieves gate control without inducing mechanical stress in the epitaxial layers
3Speed
If gate length is scaled down for high frequency operations, then frequency performance improves, but electrostatic isolation is degraded due to short channel effects, limiting gain and increasing leakage
Solution Approach 1:
The gate control mechanism transitions from vertical field (top gate) to lateral field (bottom gate). This dimensional change in field direction allows the gate to maintain electrostatic isolation and control over the channel even when scaled to short lengths, as the lateral field configuration provides better field confinement and reduced short channel effects
Solution Approach 2:
Inverting the gate to the bottom position changes the field geometry from vertical to lateral, which fundamentally improves electrostatic isolation. The lateral field configuration naturally provides better gate control and reduced leakage currents, enabling the device to maintain performance at scaled dimensions for high frequency operations
4Power
If conventional HEMT operation with vertical gate field is used, then the gm curve shows a peak due to electron density modulation, but this abrupt change results in large gm derivatives degrading linearity performance
Solution Approach 1:
Inverting the gate structure from top to bottom contact changes the field configuration from vertical to lateral. This inversion transforms the transconductance characteristic from a peaked shape (caused by vertical field-induced electron density modulation) to a more gradual curve, reducing higher-order gm derivatives and improving linearity performance
Solution Approach 2:
The invention changes the fundamental parameter of field direction from vertical to lateral. This parameter change fundamentally alters the transconductance curve shape from peaked to gradual, reducing the magnitude of gm derivatives and improving linearity while maintaining adequate transconductance values for power applications
5Device complexity
If top gate contact configuration is used, then the device structure is conventional, but junction temperature peaks at the drain end of the gate where electric field is highest, increasing with device periphery and limiting output power
Solution Approach 1:
The gate is extracted from the top surface and repositioned to the bottom of the device. This extraction removes the gate from the high-temperature region near the drain end, allowing heat to dissipate more effectively and reducing the peak junction temperature that limits output power and efficiency
Solution Approach 2:
Moving the gate to the bottom dimension changes the thermal management geometry. The gate is positioned away from the primary heat generation zone at the drain end, improving thermal dissipation pathways and reducing the temperature rise that occurs with increased device periphery
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the linearity and frequency performance of FETs by minimizing high-order transconductance derivatives and varying threshold voltages along the depth direction, leading to improved RF power efficiency and extended device lifetime.
Implementation Method 1
For GaN-based high electron mobility transistors (HEMTs) with strong piezoelectricity
Implementation Method 2
the AlGaN barrier layer comprises a first AlGaN layer and a second AlGaN layer, each having a different polarization direction
Data Source
AI summary
A FET with buried gate structures which contact an epitaxial channel layer only from the sides. The epitaxial channel layer preferably comprises multiple channel segments, the widths of which vary along the depth direction. By controlling the slope of the channel sidewalls and the distance between buried gate structures, the FET's transfer characteristics can be engineered to improve the FET's linearity.