Buried Gate Structures for GAA FinFET Leakage Control
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Solution Overview
Problem
GAA finFET devices face challenges with off-state leakage current due to drain-induced barrier lowering, which degrades device performance and requires improved gate control to mitigate short-channel effects.
Innovation Solution
The formation of buried gate structures below the bottom channel and source/drain structures in FET devices, with controlled recess depth, reduces off-state leakage current and tunes the threshold voltage by enhancing gate control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional gate structures are used in scaled-down FET devices, then manufacturing complexity is reduced, but off-state leakage current increases due to drain-induced barrier lowering
Solution Approach 1:
The patent introduces a buried gate structure positioned beneath the channel region, adding a vertical dimension to gate control. This third-dimensional gate placement (below the channel rather than only above or around it) enables new control mechanisms over carrier flow and barrier height, effectively reducing off-state leakage without complicating the manufacturing process
2Object-generated harmful factors
If gate control is enhanced to reduce short-channel effects, then off-state leakage current is reduced, but device complexity increases
Solution Approach 1:
The buried gate structure is nested within the substrate beneath the channel region, creating a hierarchical gate configuration. This nested arrangement allows the buried gate to provide additional control authority without occupying lateral space or requiring complex three-dimensional wrapping structures, thereby reducing device complexity while enhancing gate control
3Object-generated harmful factors
If threshold voltage is increased to improve device performance, then off-state leakage current is reduced, but on-state current capability decreases
Solution Approach 1:
The buried gate structure provides dynamic control capability by enabling independent adjustment of threshold voltage through the buried gate voltage. This dynamic control mechanism allows the device to optimize the balance between off-state leakage reduction and on-state current capability based on operating conditions, rather than being fixed at a single threshold voltage
Data Source
AI summary
The present disclosure describes a semiconductor device having a buried gate structure. The semiconductor device includes a substrate and a fin structure on the substrate. The fin structure includes a top portion and a bottom portion. The semiconductor device further includes a gate structure on the bottom portion of the fin structure. Multiple semiconductor layers in the top portion of the fin structure are disposed on the gate structure. The semiconductor device further includes a source/drain structure above the gate structure and in contact with the multiple semiconductor layers.