Buried Gate Dielectric Structure for Lower GIDL in Memory Cells
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Solution Overview
Problem
Gate-induced drain leakage (GIDL) increases in semiconductor devices due to the overlap between the gate electrode and impurity regions, leading to deteriorated operational reliability and interference between word-lines in different memory cells.
Innovation Solution
A semiconductor device with a gate structure that includes an upper gate electrode, a capping layer, and a first dielectric layer partially disposed between the upper gate electrode and the capping layer, along with a lower gate electrode and a dielectric layer of constant thickness between the lower gate electrode and the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a gate electrode is disposed adjacent to impurity regions in an active region, then the buried gate structure can control the semiconductor device operation, but gate-induced drain leakage (GIDL) increases due to the overlap between the gate electrode and impurity regions
Solution Approach 1:
The gate structure is segmented into an upper gate electrode and a lower gate electrode separated by a gate dielectric layer. This segmentation spatially divides the gate function, allowing the upper gate to control channel formation while the lower gate is positioned to minimize overlap with impurity regions, thereby reducing GIDL while maintaining device control capability
Solution Approach 2:
The gate structure transitions from a conventional single-layer horizontal gate to a vertical stacked configuration with upper and lower gates separated in the vertical dimension. This dimensional change allows the lower gate to be positioned at a depth that reduces overlap with surface impurity regions, effectively lowering GIDL while the upper gate maintains control over the channel
2Adaptability or versatility
If a passing gate is disposed in an isolation region, then the buried gate structure can be extended to isolation areas, but the occurrence of GIDL is exacerbated
Solution Approach 1:
The passing gate is segmented into upper and lower components with the lower gate positioned in the isolation region and the upper gate extending into the active region. This segmentation allows the gate structure to adapt to the isolation region geometry while minimizing the overlapping area between the gate electrode and impurity regions, thereby reducing GIDL in passing gate configurations
Solution Approach 2:
The lower gate electrode in the passing gate configuration is positioned at a specific depth in the isolation region where impurity concentration is lower, creating a local quality difference that reduces GIDL. The upper gate maintains its control function in the active region, allowing the structure to adapt to different regional requirements
3Volume of moving object
If a thin dielectric layer is used between the gate electrode and capping layer, then the device structure can be compact, but the effective electric field increases leading to higher GIDL
Solution Approach 1:
Instead of increasing the horizontal thickness of the dielectric layer (which would increase volume), the solution uses the vertical dimension by introducing a lower gate electrode beneath the upper gate. This stacked configuration maintains a compact overall volume while the lower gate's positioning reduces the effective electric field in the critical overlap region, thereby reducing GIDL
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The thicker dielectric layer reduces the effective electric field, lowering GIDL and avoiding interference between word-lines, while the constant thickness dielectric layer optimizes subthreshold swing and decreases threshold voltage, increasing channel ions by up to 60%.
Implementation Method 1
Forming a thicker dielectric layer in the trench may reduce the effective electric field and consequently reduce GIDL
Implementation Method 2
The dielectric layer between the lower gate electrode and the substrate can have a constant thickness, which helps to optimize the subthreshold swing and decrease the threshold voltage
Data Source
AI summary
A method for manufacturing a semiconductor device is provided. The method includes forming a trench in a substrate; disposing an upper gate electrode in the trench; disposing a first dielectric layer on the upper gate electrode in the trench; and disposing a capping layer on the first dielectric layer in the trench.