Buried Gate Structure With Fluorine Passivation for GIDL Suppression
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Solution Overview
Problem
Buried gate type transistors face challenges in achieving high transistor performance due to gate-induced drain leakage (GIDL) characteristics and threshold voltage control, which affect their reliability and efficiency.
Innovation Solution
A semiconductor device with a buried gate structure is developed, featuring a substrate with doped regions, a trench for the gate dielectric layer and gate electrode, and a fluorine-containing passivation layer to improve retention and row hammer characteristics by forming a fluorine-rich capping layer over the gate electrode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a buried gate structure is used to achieve high transistor performance, then transistor efficiency is improved, but gate-induced drain leakage (GIDL) characteristics worsen reliability
Solution Approach 1:
A fluorine-containing passivation layer is introduced as an intermediary between the gate electrode and gate dielectric layer. This passivation layer acts as a mediator that suppresses GIDL current by passivating interface states and reducing trap density at the gate dielectric-semiconductor interface, thereby improving reliability without compromising transistor efficiency
Solution Approach 2:
The patent modifies the chemical composition and physical properties of the interface between gate electrode and gate dielectric by introducing fluorine-containing materials. This changes the electrical characteristics of the interface, reducing trap density and suppressing GIDL effects, which resolves the reliability issue while maintaining high transistor performance
2Ease of manufacture
If conventional gate structures are used, then manufacturing is simpler, but threshold voltage control is insufficient
Solution Approach 1:
The gate structure is segmented into multiple functional layers: gate electrode, fluorine-containing passivation layer, and gate dielectric layer. This segmentation allows independent optimization of each layer's properties, enabling precise threshold voltage control through the fluorine-containing passivation layer while maintaining compatibility with conventional manufacturing processes
3Device complexity
If no passivation layer is used between gate dielectric and gate electrode, then device complexity is reduced, but retention and row hammer characteristics deteriorate
Solution Approach 1:
The fluorine-containing passivation layer serves as a protective intermediary between the gate dielectric and gate electrode, specifically addressing retention and row hammer issues by passivating interface states that would otherwise cause charge trapping and data retention failures in 3D XPoint memory structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the reliability and performance of buried gate transistors by reducing parasitic capacitance and suppressing gate-induced drain leakage, thereby improving retention and row hammer characteristics.
Implementation Method 1
a fluorine-containing passivation layer between the gate dielectric layer and the gate electrode
Implementation Method 2
The solution enhances the reliability and performance of buried gate transistors by reducing parasitic capacitance and suppressing gate-induced drain leakage
Data Source
AI summary
Present invention relates to a semiconductor device including a buried gate structure. A semiconductor device comprises a substrate; a first fluorine-containing layer over the substrate; a trench formed in the first fluorine-containing layer and extended into the substrate; a gate dielectric layer formed over the trench; a gate electrode formed over the gate dielectric layer and filling a portion of the trench; a second fluorine-containing layer formed over the gate electrode; and a fluorine-containing passivation layer between the gate dielectric layer and the gate electrode.