Buried Gate Oxide Structure for GIDL Suppression in DRAM
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Solution Overview
Problem
The Gate-Induced Drain Leakage (GIDL) effect in buried gate DRAMs affects performance and reliability, leading to data access errors and increased leakage current.
Innovation Solution
A semiconductor structure with a gate oxide layer and ion implantation area is designed, where the ion implantation area is positioned to increase the equivalent thickness of the gate oxide layer edge, reducing the GIDL effect while maintaining device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a buried gate structure is used to achieve high density storage, then storage density is improved, but GIDL effect increases causing performance degradation and reliability issues
Solution Approach 1:
The patent applies local quality by creating a non-uniform gate oxide layer thickness through selective ion implantation. The gate oxide layer has different thicknesses at different locations: thicker at the edges (where GIDL occurs) and thinner at the center (for better device performance). This is achieved by implanting ions laterally from the sides of the gate trench, which preferentially deposit material at the edges where the oxide layer is thinner, thereby locally increasing thickness to suppress GIDL effect without compromising overall device functionality.
Solution Approach 2:
The patent changes the physical and chemical parameters of the gate oxide layer by introducing ion implantation. The ion implantation process modifies the oxide layer's thickness distribution, composition, and electrical properties. Specifically, it changes the oxide thickness from uniform to non-uniform (thicker at edges), and introduces dopant atoms that alter the electrical characteristics of the oxide layer, thereby reducing GIDL current while maintaining capacitance for data storage.
2Productivity
If pattern dimension is reduced to increase yield, then manufacturing yield is improved, but GIDL effect becomes more severe
Solution Approach 1:
As device dimensions are scaled down to increase yield, the GIDL effect becomes more pronounced. The patent addresses this by applying local quality enhancement through selective ion implantation at the gate oxide edges. This creates localized thickness increase precisely where GIDL occurs during the scaled-down geometry, compensating for the worsened GIDL effect that results from dimension reduction while maintaining the high-density benefits of scaled manufacturing.
3Reliability
If gate oxide layer thickness is increased to reduce GIDL, then GIDL effect is reduced, but device capacitance and performance may be compromised
Solution Approach 1:
The patent resolves this contradiction by making the gate oxide layer thickness location-dependent. The ion implantation process selectively increases thickness only at the critical edge regions where GIDL occurs, while maintaining thinner thickness at the gate center region. This spatially differentiated approach ensures that reliability is improved at the edges without compromising the capacitance and switching performance that depend on the overall gate oxide characteristics.
Solution Approach 2:
The gate oxide layer is effectively segmented into different functional zones: edge regions with thicker oxide for GIDL suppression and center regions with thinner oxide for optimal device performance. The ion implantation process creates this segmentation by laterally depositing material that preferentially accumulates at the edges, thereby dividing the gate oxide into zones with different thicknesses and functions, simultaneously achieving reliability improvement and performance maintenance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The structure reduces GIDL, improves device yield and reliability, minimizes data access errors, and decreases static power consumption, extending the device's service life.
Implementation Method 1
Ion implantation is performed on the gate oxide layer to form an ion implantation area in the gate oxide layer
Data Source
AI summary
A semiconductor structure and a method for manufacturing a semiconductor structure are provided. The semiconductor structure includes: a substrate; a gate trench located in the substrate; a gate oxide layer located on a side wall and a bottom of the gate trench; and a gate conductive layer located on a surface of the gate oxide layer, a top of the gate conductive layer being lower than a top of the gate trench. The gate oxide layer includes an ion implantation area. A bottom of the ion implantation area is higher than a bottom of the gate conductive layer and lower than the top of the gate conductive layer, and a top of the ion implantation area is higher than or flush with the top of the gate conductive layer.