Buried Gate Height Equalization in Semiconductor Devices
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Solution Overview
Problem
The existing buried gate structure in semiconductor memory devices faces challenges in reducing parasitic capacitance due to height differences between cell and peripheral regions, leading to increased complexity in bit line formation and potential increases in parasitic capacitance.
Innovation Solution
A semiconductor device and method that equalize the buried gate height in the cell region to the gate height in the peripheral region by creating a step height between the two regions, using a hard mask and landing plug, and adjusting the device isolation layer depth, allowing for easier bit line and storage node contact formation while reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a buried gate structure is used in the cell region to reduce parasitic capacitance, then parasitic capacitance between gate and bit line decreases by about 50%, but a height difference is created between the buried gate and the gate in the peripheral region, requiring additional space compensation methods
Solution Approach 1:
The patent introduces a vertical dimension solution by forming a step structure in the peripheral region. Instead of horizontally expanding to accommodate height differences, the peripheral region is lowered vertically to match the buried gate level, allowing bit lines to be formed at the same level in both regions without increasing planar area.
Solution Approach 2:
The patent applies different structural treatments to different regions: the cell region maintains the buried gate structure while the peripheral region is selectively lowered to create a step. This localized modification allows the bit lines to be formed at the same level in both regions, eliminating the need for empty space compensation while preserving the parasitic capacitance reduction benefit.
2Device complexity
If empty space is provided in the cell region to compensate for height difference, then the buried gate height can be matched with peripheral region gate, but storage node contact must be formed at deeper depth, increasing difficulty in forming bit line
Solution Approach 1:
Instead of raising the buried gate level to match the peripheral gate (which would require empty space and deeper contacts), the patent inverts the approach by lowering the peripheral region to match the buried gate level. This inversion eliminates the need for deep storage node contacts and simplifies bit line formation while achieving height matching.
3Device complexity
If bit lines of cell region are formed simultaneously with peripheral region gate, then height difference is compensated, but electrode and gate electrode are formed by same material requiring barrier metal layer, making peripheral gate higher and increasing parasitic capacitance
Solution Approach 1:
The patent performs preliminary action by first forming the step structure in the peripheral region before forming the bit lines. This preliminary height adjustment ensures that when bit lines are subsequently formed in both regions, they naturally align at the same level without requiring simultaneous formation or additional barrier metal layers, thus avoiding increased parasitic capacitance.
Data Source
AI summary
A semiconductor device includes a structure in which a difference in height between a cell region and a peripheral region are formed so that a buried gate structure of the cell region is substantially equal in height to the gate of the peripheral region, whereby a bit line and a storage node contact can be more easily formed in the cell region and parasitic capacitance can be decreased. The semiconductor device includes a cell region including a gate buried in a substrate, and a peripheral region adjacent to the cell region, where a step height between a surface of the cell and a surface of the peripheral region is generated.