Buried Gate Landing Plug Segmentation for DRAM Bridge Prevention
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Solution Overview
Problem
In sub-60nm DRAM processes, forming a buried gate is challenging due to increased interfacial resistance between storage node contacts and substrates, particularly when designing bit-line contact holes, as it requires minimizing bridge formation between bit lines and storage node contacts, which complicates the process and affects device characteristics like leakage and refresh characteristics.
Innovation Solution
The method involves forming landing plugs over a substrate, etching trenches between them, partially filling these trenches with a buried gate, and then forming gap-fill layers to expose surfaces, with trimming processes to create protruding and buried portions of the landing plugs, which helps in preventing bridges between bit lines and storage node contacts by increasing the process margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the storage node contact hole and storage node contact are formed before the bit line is formed to increase process margin, then the process margin is improved, but the contact area is reduced causing increased contact resistance
Solution Approach 1:
The landing plug is divided into two distinct portions: a buried portion that provides contact area with the substrate, and a protruding portion that extends upward. This segmentation allows the buried portion to maintain contact resistance while the protruding portion provides spacing for process margin.
Solution Approach 2:
The landing plug structure transitions from a two-dimensional contact area to a three-dimensional structure with both horizontal (buried portion for contact area) and vertical (protruding portion for spacing) dimensions, simultaneously addressing contact resistance and process margin requirements.
2Object-affected harmful factors
If the bit line area is increased to prevent bridge formation, then bridge prevention is improved, but the exposed contact margin for storage node contact hole is further decreased
Solution Approach 1:
By segmenting the landing plug into buried and protruding portions, the protruding portion creates additional vertical spacing that increases exposed contact margin without requiring larger bit line areas, thus preventing bridges while maintaining manufacturing precision.
Solution Approach 2:
The landing plug protruding portions are formed in advance before bit line deposition, pre-establishing the spacing structure that prevents bridge formation between bit lines and storage node contacts.
3Reliability
If the landing plug area is increased to maintain contact resistance, then contact resistance is improved, but bridge formation between bit line and storage node contact increases
Solution Approach 1:
The landing plug is segmented into a buried portion for maintaining contact resistance and a protruding portion for preventing bridge formation, allowing both requirements to be satisfied simultaneously through spatial separation of functions.
Solution Approach 2:
The solution moves from purely horizontal area expansion to three-dimensional structure, where the protruding portion utilizes vertical space to provide spacing for bridge prevention while the buried portion maintains horizontal contact area for low resistance.
Data Source
AI summary
A method for fabricating a semiconductor device includes forming landing plugs over a substrate, forming a trench by etching the substrate between the landing plugs, forming a buried gate to partially fill the trench, forming a gap-fill layer to gap-fill an upper side of the buried gate, forming protruding portions of the landing plugs, and trimming the protruding portions of the landing plugs.