Buried Gate Structure for Semiconductor Inter-Cell Leakage Control
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Solution Overview
Problem
Semiconductor devices face inter-cell interference issues due to reduced intervals between transistors, leading to data loss as electrons can move from an on-state channel to an adjacent off-state channel, causing leakage and performance degradation.
Innovation Solution
The semiconductor device incorporates a buried gate structure with a device isolation region, featuring upper and lower active gate structures vertically spaced apart, along with a field gate structure, to prevent electron interference and enhance channel control, thereby reducing gate-induced drain leakage and improving read/write speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If intervals between cell transistors are reduced to increase integration density, then device integration density is improved, but inter-cell interference increases causing data loss
Solution Approach 1:
The gate structure is divided into multiple segments including first gate electrodes, second gate electrodes, and third gate electrodes positioned at different vertical levels. These segmented gates create isolated control regions that prevent electron leakage between adjacent cell transistors while maintaining high integration density through vertical stacking
Solution Approach 2:
The patent transitions from a planar gate arrangement to a three-dimensional vertical gate structure. By positioning gate electrodes at different vertical levels (first gate at lower level, second gate at intermediate level, third gate at upper level), the design utilizes the vertical dimension to achieve both high integration density and effective isolation of adjacent cells
2Productivity
If transistor size is reduced to increase integration, then integration density is improved, but gate control over channel becomes weaker increasing leakage
Solution Approach 1:
The gate is segmented into multiple electrode groups (first, second, and third gate electrodes) positioned at different vertical levels along the channel. This segmentation allows each gate segment to independently control specific channel regions, strengthening overall gate control and reducing leakage in scaled-down transistors
Solution Approach 2:
The gate structure employs a nested arrangement where first gate electrodes, second gate electrodes, and third gate electrodes are vertically stacked and nested along the channel direction. This nested configuration enhances the effective gate control volume over the channel region, compensating for reduced transistor dimensions
Data Source
AI summary
A semiconductor device may include a device isolation region configured to define an active region in a substrate, an active gate structure disposed in the active region, and a field gate structure disposed in the device isolation region. The field gate structure may include a gate conductive layer. The active gate structure may include an upper active gate structure including a gate conductive layer and a lower active gate structure formed under the upper active gate structure and vertically spaced apart from the upper active gate structure. The lower active gate structure may include a gate conductive layer. A top surface of the gate conductive layer of the field gate structure is located at a lower level than a bottom surface of the gate conductive layer of the upper active gate structure.