Buried Gate Structure for GAA FinFET Leakage Suppression
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Solution Overview
Problem
GAA finFET devices face challenges with off-state leakage current due to drain-induced barrier lowering, which degrades device performance and requires improved gate control to mitigate short-channel effects.
Innovation Solution
The formation of buried gate structures below the bottom channel and source/drain structures in FET devices, which reduces off-state leakage current and tunes the threshold voltage by controlling recess depth and connecting or separating adjacent buried gate structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional gate structures are used in scaled-down FET devices, then device scaling is achieved, but off-state leakage current increases due to drain-induced barrier lowering
Solution Approach 1:
The patent introduces a buried gate structure positioned beneath the channel region, adding a vertical dimension to gate control. This third-dimensional gating approach (from conventional planar or FinFET side-gating) enables electrostatic control of the channel from below, effectively suppressing drain-induced barrier lowering and reducing off-state leakage current while maintaining scaled device dimensions.
Solution Approach 2:
The gate control is segmented into multiple independent gate structures: a conventional top gate and a buried gate positioned below the channel. This segmentation allows independent optimization of each gate's electrostatic control, with the buried gate specifically targeting suppression of short-channel effects and leakage current while the top gate provides primary channel control.
2Productivity
If device dimensions are reduced to increase storage capacity and processing speed, then performance improves, but manufacturing complexity increases
Solution Approach 1:
The buried gate structure is formed prior to channel formation through selective epitaxial growth in recessed regions. This preliminary action establishes the gate control architecture before subsequent processing steps, simplifying the overall manufacturing sequence by integrating the buried gate formation into existing epitaxial and etching processes rather than adding separate fabrication stages.
Data Source
AI summary
The present disclosure describes a semiconductor device having a buried gate structure. The semiconductor device includes a substrate and a fin structure on the substrate. The fin structure includes a top portion and a bottom portion. The semiconductor device further includes a gate structure on the bottom portion of the fin structure. Multiple semiconductor layers in the top portion of the fin structure are disposed on the gate structure. The semiconductor device further includes a source/drain structure above the gate structure and in contact with the multiple semiconductor layers.