Buried Gate Semiconductor Memory Reducing Parasitic Capacitance
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Solution Overview
Problem
High-integration semiconductor memory devices face increased parasitic capacitance due to reduced physical distances between conductive elements, leading to reduced operational stability, data transfer issues, and reading errors, with existing methods struggling to maintain process margins for forming storage node and bit line contact plugs.
Innovation Solution
A semiconductor memory device manufacturing method involving a buried gate structure with a buried word line and carefully controlled insulation and conductive layer formation to reduce parasitic capacitance, ensuring a process margin for forming bit line and storage node contact plugs, and using metal for bit line and contact plug formation to increase physical distances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the degree of integration is increased by reducing the size of constituent elements and connection wires, then productivity and integration density are improved, but resistance increases and operational stability deteriorates
Solution Approach 1:
The patent transitions from planar wiring to three-dimensional stacked wiring structure. Word lines and bit lines are arranged in multiple layers vertically, allowing data transfer paths to be established in the vertical dimension. This reduces the horizontal distance between interconnected elements while maintaining adequate separation between conductive paths, thereby reducing resistance without increasing parasitic capacitance.
Solution Approach 2:
The patent divides the wiring structure into multiple discrete conductive layers (first word line layer, second word line layer, first bit line layer, second bit line layer) separated by insulating layers. This segmentation allows independent optimization of each layer's routing and reduces electromagnetic interference between adjacent conductors by maintaining proper spacing through the insulating structures.
2Reliability
If the cross-sectional size of word line or bit line is maintained, then operational stability is preserved, but parasitic capacitance increases due to reduced physical distance between word line and bit line
Solution Approach 1:
The patent utilizes vertical stacking to separate word lines and bit lines into different height levels. The insulating layers positioned between conductive layers increase the physical distance between word lines and bit lines in the vertical dimension, thereby reducing parasitic capacitance while maintaining adequate connection strength and signal integrity.
Solution Approach 2:
The patent introduces insulating layers as intermediary structures between conductive elements. These insulating layers act as dielectric barriers that reduce the electric field coupling between adjacent word lines and bit lines, thereby minimizing parasitic capacitance effects while allowing the conductors to remain in close proximity for efficient signal transfer.
3Reliability
If the size of capacitor in unit cell is increased to compensate for increased parasitic capacitance, then data transfer reliability is improved, but device complexity increases and integration density decreases
Solution Approach 1:
The patent reduces parasitic capacitance through three-dimensional wiring architecture, which eliminates the need to increase capacitor size for compensation. By establishing proper spatial separation between conductors in the vertical dimension, the system maintains data transfer reliability without requiring larger capacitors, thereby preserving integration density and avoiding increased device complexity.
Data Source
AI summary
A semiconductor memory device and a method for manufacturing the same are disclosed, which reduce parasitic capacitance generated between a storage node contact and a bit line of a high-integration semiconductor device. A method for manufacturing a semiconductor memory device includes forming a buried word line in an active region of a cell region, forming an insulation layer in the cell region and a lower electrode layer of a gate in a peripheral region so that a height of the insulation layer is substantially equal to that of the lower electrode layer, and providing a first conductive layer over the cell region and the peripheral region to form a bit line layer and an upper electrode layer.